Cadence has released a chip routing tool for digital, mixed signal and analogue designs at 65nm and below.

Called Precision Router, it is built on the firm’s ‘space-based’ architecture, which allows for incremental optimisation of designs without extracting physical properties and net-to-net relationships.

“For every shape we store its relationship to its neighbours, so if we manipulate a shape we can incrementally update our data model,” said Wilbur Luo, group product marketing director in Catena, Cadence’s internal technology incubator.

“All the connectivity, all the rules, each shape retains all that information too. So you don’t have to re-run an extractor and rediscover timing values,” he said.

The tool includes support for speciality mixed-signal routing, in-core electrical analysis, and optimisations for design for manufacturing and design for yield.

Constraints can be supplemented through Open Access with, for example, recommended rules from a foundry. Cadence said it helps designs converge faster, outputting DRC errors that “exactly match a sign-off quality checker”.

The firm has used Precision Router in tape-outs with four foundries, including one design at 45nm.

Cadence