Despite opening up their interconnect for multiple processors on a chip, Intel and AMD need to do more to meet the performance and power requirements future systems will need, according to a leading processor core provider.

Intel has shown a prototype of 80 cores on a chip, and provided direct interconnect between the cores through its Geneseo programme in a similar way to AMD’s HyperTransport interconnect.

“HyperTransport has a tremendous following but they are the PC processors on the chip and at a much more complicated level with protocols, whereas point to point connections don’t need protocols other than a two wire handshake,” said Steve Leibson, v-p of marketing for configurable core designer Tensilica on his tutorial at the SAME conference in the South of France this week.

The ITRS semiconductor roadmap sees chips with 32 processing elements next year, rising to 79 in 2010 and 878 processing elements on one chip by 2020.

“To me, opening up this capability isn’t the processor with the direct connection,” Leibson said. “Without configurable processors, none of this works.”

Leibson sees a return to building systems that look like the algorithm they want to implement, connected by simple point to point links. “This is precisely what we are doing with Epson in Japan right now on a relatively inexpensive inkjet printer,” he said.

“They have six algorithms for colour transformation and scaling etc, and hook those algorithms directly with six cores configured to those algorithms. The system prints pages three times faster than before and uses just 2.5W,” he added.

“It comes as a big shock to people when they realise they have been struggling to map an algorithm into RTL and then onto C running on a general processor when they don’t have to – they can just map the C code onto the core that is optimised for it,” said Leibson.