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Tuesday 14 October 2008
Components
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|NewsletterMicroprocessors and DSPs
Multi-processor device takes on FPGAs
Thursday 21 June 2007
Researchers at Stanford University are trying to find a middle ground between custom multi-processor designs and highly reconfigurable FPGA devices with high performance extensions where the processor becomes the new building block of the system.
The Chip Multiprocessor Generator developed by Alex Solomatnikov and his team allows multi-chip systems to be put together easily, significantly reducing the non-recurring engineering (NRE) costs but still allowing the system to be optimised and produce a small die.
The system consists of tiles, each with two Tensilica processor cores, several reconfigurable memory blocks, and a crossbar connecting them. Tiles are placed in groups of four, forming Quads.
Tiles in the Quad are connected to a shared protocol controller and the Quads are then connected to each other and to the off-chip interfaces using an on-chip network.
Because the system uses the Tensilica configurable processors, additional instructions can be added to accelerate specific functions.
“We can add custom functionality units to provide performance and the unused parts can be removed during synthesis,” said Solomatnikov, speaking at the Design Automation Conference in San Diego. “Designers will configure processors, and local memory as gates and write their software, not gates. The processor becomes the new gate and this removes the overhead of reconfigurable logic.”
The team has developed two test chips, one with four tiles each with two processors with VLIW extensions and 16 reconfigurable units per tile that measures 50mm sq. in a 90nm process and a smaller version, still with four tiles but only one processor and eight reconfigurable units pert tile. This measures 13mm sq. in a 90nm process said Solomatnikov.
The Chip Multiprocessor Generator developed by Alex Solomatnikov and his team allows multi-chip systems to be put together easily, significantly reducing the non-recurring engineering (NRE) costs but still allowing the system to be optimised and produce a small die.
The system consists of tiles, each with two Tensilica processor cores, several reconfigurable memory blocks, and a crossbar connecting them. Tiles are placed in groups of four, forming Quads.
Tiles in the Quad are connected to a shared protocol controller and the Quads are then connected to each other and to the off-chip interfaces using an on-chip network.
Because the system uses the Tensilica configurable processors, additional instructions can be added to accelerate specific functions.
“We can add custom functionality units to provide performance and the unused parts can be removed during synthesis,” said Solomatnikov, speaking at the Design Automation Conference in San Diego. “Designers will configure processors, and local memory as gates and write their software, not gates. The processor becomes the new gate and this removes the overhead of reconfigurable logic.”
The team has developed two test chips, one with four tiles each with two processors with VLIW extensions and 16 reconfigurable units per tile that measures 50mm sq. in a 90nm process and a smaller version, still with four tiles but only one processor and eight reconfigurable units pert tile. This measures 13mm sq. in a 90nm process said Solomatnikov.
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