Programmable logic will soon be implemented in "3D" chip designs if the claims of California firm Tabula are realised in silicon.
The company is developing programmable logic devices based on a new programmable logic architecture incorporating logic, memory, interconnect fabric and compiler, which can reconfigure so rapidly logic elements can be re-used in the same circuit design.
Called Spacetime, the architecture will be used to create programmable logic devices with 3D interconnect at “multi-GHz” frequencies according to the company.
The third dimenion being time as the device reconfigures.
The first devices will be fabbed on a 40nm CMOS process. The architecture consists of a fabric of what the company called “folds”.
“Each fold performs a portion of the desired function and stores the result in place. When some or all of a fold is reconfigured, it uses the locally stored data to perform the next portion of the function,” said Tabula.
The compiler that automatically maps standard RTL into Spacetime.
“The key to Spacetime and its many advantages is resolving the interconnect problem intrinsic to FPGAs,” said Steve Teig, Tabula’s president and CTO.
“Almost 90% of the core area of FPGAs is devoted to the implementation and control of interconnect. If you’re going to achieve a breakthrough in programmable capability and affordability, you have to make the interconnect more efficient, and that’s what Spacetime does,” said Teig.
Tabula was founded by EDA pioneer Steve Teig and is led by Dennis Segers, former CEO of Matrix Semiconductor and former Senior Vice President and member of the board of directors at Xilinx.
Tabula is developing a family of programmable 3D devices.
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