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Optimising both static and dynamic power is key to low-power ICs - Rhines

David Manners
Wednesday 01 April 2009 17:50

Read our full Globalpress Summit Conference coverage

See also: Q5 Interview - Wally Rhines, CEO of Mentor Graphics

The growth of power consumption in electronics products is growing at 35 per cent a year and server farms are consuming 60bn kilowatt/hours a year and growing at 50 per cent. Something has to be done, said Wally Rhines, CEO of Mentor Graphics, opening the third day of the Globalpress Summit Conference in San Francisco today.

As design moves up towards the system level, the opportunities to reduce power improve, according to Rhines.

"The higher you go in abstraction, the more control you have over reducing power", said Rhines, the trick being, he added: "The simultaneous optimisation of static power and dynamic power."

Asked which is a worse problem, Rhines replied: "Static power as a percentage of the total power is increasing faster, and becoming a worse problem, more quickly than the dynamic power. But dynamic power is still a problem because, as you shrink, you increase the capacitance."

Next week Mentor is to launch a place-and-route system with concurrent multi-corner, multi-mode (MCMM) power states and timing closure for optimal quality of results and fast turnaround time.

It will have a flexible architecture for automated multi-voltage design flow and concurrent optimisation of leakage and dynamic power, timing and signal integrity across multi-corner multi-mode (MCMM) scenarios delivering, says Mentor, 2-3X faster design and 30 per cent power savings.

See also: Mannerisms, the blog of David Manners. Updated twice daily, it's the distinctive, entertaining, authoritative and never dull commentary on the semiconductor industry, from someone who knows. Sign up for the Mannerisms eNewsletter.



 

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