A new wave of technologies is being brought on stream to
help engineers sustain design productivity when confronted by
smaller geometries, says Wally Rhines of Mentor Graphics
A unique convergence of intense pressures is threatening the
viability of “cheaper, smaller, faster” that has driven
the high tech industry for decades. Thanks to ever smaller
geometries, designs have evolved from single- or multi-block
functional units into massive systems targeted at complex
applications such as wireless, consumer, computing, and industrial.
Industry analysts predict that by 2010 mainstream designs will
most likely include geometries of 32 nanometres with 100 billion
transistors on a die, as well as designs encompassing multi-chip
systems. These systems will not only support digital and analogue
circuitry, but radio frequency (RF) as well for wireless
communications.
Issues such as static current leakage and timing closure at
these smaller geometries further complicate the design task and
limit manufacturing yields. Power issues are also emerging with
passive power approximating or even exceeding active power,
threatening most designs’ power and thermal budgets.
All this is leading to design and verification overload, pushing
development costs up significantly. In response, the EDA industry
is bringing a new wave of technologies on stream to help engineers
sustain design productivity by addressing the hot spots in
nanometre design.
Raising the level of front-end abstraction
As mainstream design moves squarely into the nanometre realm,
performance, power and cost issues all need to be carefully
balanced. That requires evaluating multiple architectures to arrive
at the optimal approach for a particular end system. However, most
hardware engineers still rely on the traditional, iterative RTL
approach and cannot afford the extra month or two often required
for rewriting the thousands of lines of RTL just to explore a
different architecture.
In the past two years, the EDA industry has introduced new tools
that raise the level of abstraction for front-end design, finally
delivering on the promise of ESL for design, synthesis, and
verification. Design tools based on the simulation and synthesis of
C representations, such as our Catapult C algorithmic synthesis
product, allow hardware engineers to design, automatically
synthesise and verify hardware, leveraging the same untimed C++
source typically generated by system designers. The ability to work
at a far more productive abstraction level frees the design team to
explore architectural tradeoffs and fine tune designs for optimal
size, power and performance.
Getting the best out of functional
verification
With millions of gates and interactions to examine, verification
is now consuming the lion’s share of a design team’s
time and resources. A recent study from Collett International
Research reveals that 49 per cent of design engineering time is
focused on verification. Increasing complexity will only exacerbate
the problem.
In response, the EDA industry is driving the biggest methodology
shift in verification since the inception of HDL simulation. Design
teams are adopting a host of new methodologies - assertion-based
verification, coverage-driven verification, and widespread use of
automatic testbenches - made possible by the availability of
standard, multi-vendor supported languages. The objective for this
cavalcade of new techniques is the seamless support of the same
verification environment from C++ and RTL to emulation.
Using assertion-based verification (ABV), verification engineers
can more effectively test a design to ensure the design matches its
functional specification. When combined with functional coverage
capabilities in a scalable verification environment such as the new
System Verilog verification products now coming to market engineers
finally have a means to track the effectiveness of their
verification efforts. The result is coverage-driven verification,
in which designers use feedback from testing to target their
successive tests, resulting in greatly improved productivity and
effectiveness.
In addition, these tools offer designers a methodology for
easily implementing a ‘golden source’ from the
algorithmic level of abstraction down to technology-specific RTL.
This significantly streamlines the verification effort, eliminating
the need to re-create the testbench at the HDL and hardware
level.
Paving the way to improved yield
Even as design and verification get more complex, the back-end
physical design is demanding more attention. In the nanometre
realm, sub-wavelength lithography processes are introducing new
yield loss mechanisms at a rate, magnitude, and complexity large
enough to require dramatic improvements in tools and methodologies.
With defects per million rates increasing, designers and
manufacturers are aggressively looking for ways to enhance yield
outcome.
The EDA industry is developing new technologies that allow
designers to consider and optimise for manufacturing at each stage
of the design, verification, tapeout and test process. One of the
most fundamental changes is the integration of DFM and DFT flows,
especially in closing the loop between manufacturing and design.
DFM-oriented test uses DFM rules, recommendations, and guidelines
to optimise test quality. Analysis of test data from manufacturing
test creates a true goldmine of information for calibrating
today’s largely qualitative DFM rules and computing yield
sensitivity functions.
The drive towards DFM will lead ultimately to an integrated
back-end platform incorporating technologies that allow the
designer to anticipate the effect on chip layout of the subsequent
resolution enhancement features, as well as automated evaluation
and yield enhancement of designs.
The heat is on
The EDA industry is working hard to assist the semiconductor
industry at the 90nm and 65nm nodes and below, developing new
tools, methodologies and flows. The goal, however, remains the
same: continued reduction of the time and cost of creating
next-generation designs. Raising the level of design abstraction,
streamlining verification and improving yield with advanced DFM and
test strategies should go a long way towards achieving that goal
even as gate counts climb into the millions and deep submicron
effects threaten yields.
Wally Rhines is chairman and CEO at Mentor Graphics
www.mentor.com