We bring together the news and technical information on the design and manufacturing of hardwired ASICs (application specific integrated circuits) and single-function, off-the-shelf ASSPs (application specific standard products).
Issues to be considered include the escalating costs of ASIC/ASSP design and verification, and the new business models which that is spawning.
Cost of designing a leading-edge ASIC
While the cost of designing a leading-edge ASIC has crept up to $40m, new design house business models are taking all the technical and financial risk out of having an ASIC designed by, effectively, taking a customer's spec and selling finished chips back to the customer.
Another new model which could help defray the huge costs of design is the 'Design Fab', or 'Logic Fab', model where large chunks of the design process, like verification, are contracted out to third parties in less costly economies.
The phenomenon has led to a big increase in design-related activity in India, Vietnam and mainland China.
Foundries
We also seek to present, in the latest news, information from the foundries. This will include the timing of the issue of design rules for new processes, details of shared 'Multi-Project' wafer runs, specifications and timings of new processes and other foundry announcements.
The intention is also to give news of the rate at which new designs are being spun in the foundries, and other information which can help to give an indication of the success of new processes.
This page will also be covering news of the EDA industry and technical articles covering the industry's evolution to higher levels of design abstraction and greater automation of the design flow.
We will also cover the entrepreneurial side of the EDA industry, looking at the new start-up companies.
So this is the place where news and information on ASIC/ASSP design tools, design houses, and foundry manufacturing issues all converge.
ELECTRONICS WEEKLY NEWS ON ASICS
Synplicity buys Asic prototyping specialist
Synplicity has agreed to acquire Hardi Electronics, a developer of off-the-shelf Asic prototyping boards, for $24.2m.
ARM-based structured Asic gets IAR development support
Structured Asic supplier eASIC and embedded tool firm IAR Systems have announced the availability of the e926 development kit for designing ARM926EJ-based embedded systems.
Is the Asic over?
"Can anything save Asic?" was the question asked at a panel session at the Globalpress Summit meeting in Monterey.
ChipX eyes embedded Asics with Oki deal
ChipX, as specialist supplier of lower cost structured Asic devices, has radically broadened its business by acquiring a standard cell and embedded array Asic design capability. The firm has signed an agreement to acquire the US-based Asic business of Oki Semiconductor.
Quicklogic on the trail of 'virtual ASSPs'
Quicklogic, the antifuse FPGA company, is moving away from being a supplier of generic programmable arrays to being more of a supplier of ‘virtual-ASSPs’.
Asic firm eSilicon is taping-out two chips a month
Asic design and production services firm eSilicon is taping out two chips a month, is close to breaking even and has plans for an IPO next year.
Freescale, ELMOS partner for intelligent auto ASSPs
Freescale Semiconductor and ELMOS Semiconductor have teamed up to develop multi-chip products to embed a higher level of intelligence into next-generation automotive systems.
Fabless Key ASIC tries new business model
Maybe the world isn't beating the bushes to find another fabless-ASIC company. But start-up Key ASIC believes that it has a model—an application-specific approach—that's just different enough to make a place for itself beside the relative giants, such as eSilicon and OpenSilicon.
Synplicity exits Asic, as LSI Logic fallout continues
LSI Logic's recent withdrawal from the structured Asic market continues to sent ripples through the industry, with EDA firm Synplicity now ending synthesis support for the sector.
Structured Asic not dead, despite LSI's exit
Despite LSI Logic's announcement earlier this week that it would be leaving the budding structured Asic market, analysts believe the sector still has a future.
Structured Asic market gains steam
LSI Logic has begun revving up its marketing pitch on RapidChip, a sign that the market for programmable Asics is finally beginning to catch on.
Structured Asic entering boom times
Worldwide merchant market dollar shipments of structured Asic products are forecast to soar from the $210m reached last year to $2.53bn by 2009.
Asic player re-routes to EDA
Physical design tool company Silicon Design Systems (SDS) is relying on its old Asic history to produce its first product.
Asic to match FPGA in design time
LSI Logic is bidding to match the short design cycles typically achieved with FPGAs with its low cost platform Asic products.
Custom Asic market not in decline, claims LSI Logic
LSI Logic has made a strong rebuttal of claims that the market for full custom Asic devices is in long term decline.
Asic firms facing ruin by move to 300mm fabs
ASIC manufacturers will be made uncompetitive by the shift to 300mm wafer fabs, according to Xilinx's chief technical officer, Kris Chellam during a talk at the European Semiconductor Conference in London last week.
ELECTRONICS WEEKLY ASICS-RELATED FEATURES
ASIC prototyping: make versus buy
IC designers often spend as much as 60 to 80 per cent of their time simply verifying designs, and that percentage is growing.
The FPGA question for ASIC engineers
Over the last 10 years, FPGA vendors have made great strides in overcoming the shortcomings of FPGAs and taking share from the ASIC market.
International challenges face ASIC-design managers
With the emergence of IC foundries in Taiwan, Singapore, and mainland China over the last decade and an abundance of relatively inexpensive engineering resources in India, eastern Europe, and mainland China now available, ASIC and SOC (system-on-chip) design is becoming a global effort.
Running an FPGA at ASIC speed
The hardware-emulation team at Texas Instruments is getting word about its next project: developing a prototype of the modem of a baseband-processor ASIC for next-generation wireless handsets.
ELECTRONICS WEEKLY BLOGS ON ASICS
Taken from Mannerisms - ruminations on the electronics industry by David Manners, Senior Components Editor on Electronics Weekly
The Ten Year ASIC Design Cycle
Is there a design crunch coming up? Well, yes there always seems to be a design crunch coming up, but this time it’s a really mega-crunch, according to Kazuyoshi Yamada, the vice president and general manager, Custom SoC Solutions Unit, of NEC Electronics America.
ASIC Development a Doddle
ASIC development is a simple business with an 88 per cent likelihood of delivering the chip on time, and a 94 per cent chance of getting it right first time.
ASIC Design Expertise Open to All, says Wally Rhines
A new breed of specialised ASIC companies has levelled up the design playing field, so that small companies can compete on equal terms with large companies, according to Wally Rhines, CEO of Mentor Graphics.
ASIC Industry a Disgrace
The ASIC industry is a disgraceful business which, if measured by the standards applied to other industries, deserves to have been killed off long ago.
ELECTRONICS WEEKLY Q5
Q5 - Carlo Rebughini, Austria Microsystems
Electronics Weekly puts its questions to an industry figure: Carlo Rebughini, vice-president of sales at Austria Microsystems
OTHER RESOURCES ON ASICS
Alchip
VeriSilicon
eAsic
Freescale ASICs
Toshiba ASIC & Foundry
ASIC (Wikipedia)