Support from two of the big three EDA vendors, added to uncertainty over how Cadence will proceed after acquiring Verisity and its e language, is driving adoption of SystemVerilog throughout the industry, according to Mentor Graphics.
“In this industry it will take two of the three big vendors to back something before it takes off,” said Robert Hum, v-p and general manager of design verification and test division at Mentor.
“Vera [the verification language] was backed by only Synopsys, so it did not become the industry standard. E, while it was independent, was kind of growing but now that Cadence owns it, it will be isolated.”
Hum said the emergence of verification languages in recent years had not affected the underlying design methodology. The same number of functional bugs make it into silicon – verification just reduces the time spent debugging the chip.
“The industry has been stagnating vis-a-vis methodology shifts for a while,” said Hum. “We’ve had RTL- based verification since the early 1990s, before that it was gate-level.”
Although assertions are increasingly establishing themselves as a powerful methodology for verification, they are hampered by the lack of an industry standard. Mentor and Synopsys are backing SystemVerilog as the language to change that.
“PSL has been there for a while, but PSL is not integrated with a simulator,” said Hum. “Vera was proprietary, e was proprietary, and SystemVerilog takes the best of both of those and creates a public standard out of it.”
Last month, Mentor announced a simulator for SystemVerilog, under its new Questa brand. The availability of that tool should drive uptake of the language further, according to Modesto Casas, head of corporate business development at coverage tool specialist TransEDA.
“I think the challenge will be whether customers will adopt assertion-based verification quickly enough,” added Casas.
“The actual SystemVerilog language is not the whoop-dee-doo deal,” continued Hum. “The whoop-dee-doo deal is that there’s a methodology that is embodied inside SystemVerilog that will help the community to develop silicon with fewer bugs."
"The methodology is assertion driven verification and coverage driven verification.”
An indication of the progress of SystemVerilog comes from the traffic Mentor has seen to its website from people downloading the beta of its simulator.
“The beta activity we had on SystemVerilog was larger than the cumulative beta activity with the last five releases of ModelSim, and we have over 140,000 licences [of ModelSim] out there,” said Hum.
www.eda.org/sv
www.mentor.com
www.systemverilog.org
www.transeda.com