Elpida and Spansion have produced prototype 4Gbit trapped-charge flash memories made using the Spansion Mirrorbit technology. Sample chips are scheduled for Q4 and mass production for Q1 2011.
"Elpida has obtained good chips from its first trial lot of charge trap NAND flash memory,” says Elpida CEO, Yukio Sakamoto, “our preparations to manufacture our NAND flash memory as soon as possible are well underway.”
The chips, which run off 1.8V, were fabbed at Elpida’s Hiroshima plant.
The problem with Mirrorbit, trapped-charge technology is that it has always lagged behind traditional floating gate flash n density. Leading NAND suppliers are already producing 64Gbit devices.
The Spansion-Elpida 4Gbit is a single level cell (SLC) device. Spansion-Elpida could move to two-bit-per-cell (MLC) technology, but only at the expense of slower write speed and a reduction in the number of programming/erase cycles from 100,000 for SLC to 30,000 for MLC.
The process used to make the chip is not disclosed, so it’s impossible to say whether higher densities are obtainable by migrating to a better process.
However, the process is quite likely to be Elpida’s 32nm process which delivers a write speed of 6-8Mbytes per second.
Spansion says the fewer process steps used in manufacturing Mirrorbit make it 20% to 40% cheaper to manufacture than traditional floating gate flash.
The main selling point for Mirrorbit, trapped charge, technology is that it is scalable to 18nm. At one time it was thought floating gate wouldn’t be viable below 32nm, but Toshiba recently announced it was producing floating gate NAND on a 24nm process.