Imagination Technologies has announced its new META HTP multi-threaded processor IP core family which the firm says improves the performance of its META2 architecture cores beyond that of DSP and RISC cores.
META HTP allows the overlapped execution of multiple threads, enabling multiple time-critical DSP-rich applications and non real-time general purpose tasks to run concurrently on the same processor, reducing power consumption and silicon area whilst increasing throughput.
META HTP implements a longer pipeline, enabling it to achieve higher clock speeds ranging from 360MHz in 130nm to 500MHz in 90nm, and up to 700MHz in 65nm process using standard cells together with high speed SRAM macros for cache.
Although longer pipelines normally reduce performance per MHz, META HTP includes additional architectural features to compensate including a return address cache and branch prediction table support.
A four threaded META HTP delivers up to 1552 Dhrystone MIPS in a 65nm process.