Researchers in the Electro-Optics Center (EOC) of Pennsylvania State University have produced 100mm graphene wafers.
Using silicon sublimation, David Snyder and Randy Cavalero heated silicon carbide wafers in a physical vapour transport furnace until the silicon migrated away from the surface, leaving behind a layer of carbon that formed into a one- to two-atom-thick film of graphene on the wafer surface.
According to EOC materials scientist Joshua Robinson, RF fets have been made on the wafers.
The highest performance graphene transistors are made on graphene flaked from lumps of graphite and stuck to substrates.
Transistors made on graphene formed on the surface of substrates have so far been poor performers compared to those on flaked graphene.
EW has not, so far, been able to establish the electron mobility of the EOC wafers.
"Attempts are being made to improve the electron mobility of the Si-sublimated wafers to nearer the theoretical limit, approximately 100 times faster than silicon," said the EOC.
That will require improvements in the material quality and device design, said Robinson, but there is significant room for improvements in growth and processing, he believes.
In addition to silicon sublimation, the EOC is attempting to develop a non-sublimation synthesis route for wafer diameters exceeding 200mm.
First discovered in 2004 at the University of Manchester, devices made in graphene could one day be 100 times faster than those in silicon.
Two years ago, Manchester broke the transistor size record using graphene.
A 100mm graphene wafer with 75,000 devices and test structures.
Each square pad is 100um across.