TSMC claims to have the first functional 65nm Multi-Time Programmable (MTP) Non-Volatile Memory (NVM) process technology.
The 2.5V technology incorporates process-qualified MTP IP blocks jointly developed with Virage Logic.
"It is the first 2.5 volt MTP process, breaking the heretofore 3.3 volt baseline barrier. It eliminates the need for an external EEPROM currently in many systems applications, thereby reducing power, area and costs while increasing data security," said TSMC.
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Built on TSMC's 65nm Low Power (LP) process, the technology features up to 8k bits memory size. This is designed to be suitable for small memory requirements associated with MP3 music downloadable digital rights management, RFID devices, fingerprint identification applications, and pre-paid cash or phone cards.
The 65nm MTP process is built up to 10 metal layers using copper low-k interconnects and nickel silicide transistor interconnects. The technology is fully logic-compatible and the NVM memory requires no additional processes or masks.
Devices built using the process will support full read and program operations across temperatures ranging from -40 degrees C to 125 degrees C, with minimum 10-year data retention at 125 deg C.
"We are convinced this 65nm process is well suited for applications that require a small memory footprint on a leading edge manufacturing technology," explains Jason Chen, v-p worldwide sales and marketing for TSMC.
TSMC said it has shipped over 700,000 12-inch wafers since the 65nm process was introduced in 2006.
The full 65nm process node includes logic, mixed-signal, R/F, and high-density memory options and supports a broad range of computing, communications, and consumer electronics applications.