A bigger effort needs to be made to increase the level of abstraction in IC design, reckons Colin Dente, CEO of Akya, the reconfigurable logic specialists. “If an effort is not made, it won’t happen”, says Dente
Akya has a technology called Akya Reconfigurable Technology (ART) which allows you to increase the abstraction level. Compared to conventional RTL, ART halves design and verification time.
Akya is working with the No.1 EDA player, Cadence, to develop the technology within the Cadence ‘C to Silicon’ design flow. Akya claims ART delivers a ‘massive’ power and area overhead saving compared to hard-wired solutions.
“High level synthesis is a technology that is now becoming mature”, says Dente, “the emerging TLM (Transaction Level Modelling) processes will make a huge improvement to productivity. Improved verification times bring a massive reward.”
The problem with conventional design flows is that it takes a long time to get down to the RTL level which is the earliest point in the design flow at which you can do meaningful verification. What TLM delivers is an executable design at an earlier stage in the design process.
“Compared to conventional design flows,” says Dente, “TLM improves performance by one or two orders of magnitude – 10X to 100X in the time it takes to do verification.”