Despite the set-back of the Crolles 2 partners going to other sources for core microelectronics process technology, the French government has said it will continue subsidising Crolles, according to a statement from the Elysee Palace, the office of French president Nicolas Sarkozy.
When Sarkozy’s predecessor, Jacques Chirac, opened Crolles 2 in 2003, its brief was to develop basic, core CMOS process technology.
The French government was underwriting 40 per cent of the Crolles 2 $250m annual budget in tax concessions, leaving the three companies paying $50m each, somewhat less than ST and Freescale are now paying IBM for core CMOS process technology.
The French government said it has studied ST’s plans for development of the site between 2008 and 2012, and is prepared to continue subsidising Crolles at a level which is to be negotiated.
Crolles is more than an R&D site. The Crolles 2 manufacturing facility is ST’s only 300mm fab, and is capable of producing 2,500 wafers per week, expandable to 2,800 wafers per week, and Crolles 1 can produce 6,500 200mm wafers a week.
The focus of basic process research in Europe has now switched from Crolles to IMEC, the Belgian R&D house. "IMEC has been a huge success story. It has almost taken over from what Bell Labs was," says Malcolm Penn, CEO of analysts Future Horizons, "it’s in every programme you could ever imagine. At 32 nm and below these guys are driving the world. Every DRAM at 32 nm and below will be using IMEC technology."
Earlier this year, Powerchip Semiconductor of Taiwan, the world’s sixth largest DRAM manufacturer, joined IMEC’s DRAM R&D consortium which includes all the major manufacturers: Samsung, Micron, Elpida, Qimonda and Hynix.
The rationale for them all going to IMEC is, according to Professor Gilbert Declerk, CEO of IMEC: "They all have the same problems."
IMEC leads the world on both of the competing approaches to 32nm and 22nm lithography: double-patterning immersion lithography, and EUV.