Mentor Graphics has made a crucial update to Catapult C, its
high level synthesis tool, adding the option of SystemC as a design
language.
Until now the tool used ANSI C++ for entering designs, with
Verilog or VHDL as the output.
With the new version, Catapult takes C++ or algorithmic systemC
as its input and progressively refines the design.
Stages of refinement are untimed SystemC, timed SystemC,
cycle-accurate SystemC and RTL. Each stage adds more detail, but
reduces simulation speed.
“We believe that any new methodology must achieve at least
10x improvement in productivity,” said Shawn McCloud, product
manager for Catapult at Mentor.
Compared to RTL, each higher level of abstraction raises the
simulation speed by a factor of ten, claimed McCloud, making the
algorithmic level 10,000 times faster than RTL.
Catapult allows different parts of a design to exist at
different stages of refinement, useful during simulation. The tool
automatically creates ‘transactors’ which mediate
between, for example, an untimed section and a cycle-accurate
section of the design.
This also makes it easier to add in legacy blocks and third
party IP.
“You can reuse the original C++ sequential testbench all
through the design process, even to RTL,” explained
McCloud.
Mentor is pushing to use C as a reference point for design:
“The best approach is to start with a single golden
source,” said McCloud.
www.mentor.com