You are in:  Components | FPGAs & Asics

Sign-up for newsletters:

Electronics Weekly newsletters - Sign up for Made By Monkeys, Mannerisms, Gadget Master and Daily and Monthly newsletters

Read The Magazine

Latest Issue: 8 - 14 Feb, 2012
Get Electronics Weekly

Has Actel solved Cortex-M3 in FPGA conundrum?

Friday 05 March 2010 09:59

Actel believes it has overcome the problem of getting a hardware processor core to operate efficiently in tandem with FPGA gates.

To do this the programmable logic supplier has designed a complete microcontroller subsystem built around a hardwired ARM Cortex-M3 processor and embedded it with its flash-based ProASIC3 FPGA fabric.

It has also added programmable analogue functions such as ADCs, DACs and comparators. 

The result is the SmartFusion range of mixed-signal programmable devices, which increases the performance specification of the firm’s four-year-old Fusion family of mixed-signal FPGAs, which included a softcore ARM Cortex-M1 processor.

Softcore processors have proved popular with FPGA designers because their implementation is straight-forward and efficient in the FPGA fabric. Hardcore processors add more performance but can introduce bus interface issues.

Actel believes it has solved the compatibility issues. Rich Kapusta, vice-president of marketing and business development at Actel, said the key is that SmartFusion includes hardwired processor peripherals as well as the 100MHz Cortex-M3 core.

This is made possible by Actel’s flash-based FPGA architecture, which differs from the more commonly used SRAM-based technology.

“The flash process allows us to add the whole MCU subsystem, including flash memory and configuration blocks,” Kapusta told EW.  

For the crucial area of processor/FPGA communications, the company has used a multi-layer AHB matrix with a data throughput of up to 16Gbit/s.

There is also a full 10/100 Ethernet MAC with RMII interface.

The CPU also has 512kbyte flash memory, 64kbyte SRAM and an eight-channel DMA controller.

According to Kapusta, the FPGA’s 60k to 500k system gates, 350MHz performance and up to 204 I/Os can be used to provide “real hardware co-processing” in target applications such as motor control and display drivers.

“You can build in hardware and as many UARTs and SPIs as you require,” said Kapusta.    

This is a true mixed-signal device and there are programmable elements including three 12-bit ADCs with up to 600ksample/s sampling rate and three 12-bit first order sigma delta DACs, along with comparators, voltage and temperature monitors.

See: Xilinx brings ARM Cortex and AMBA to its FPGAs

 

Comments powered by Disqus

Related Jobs

Resources