TSMC will wait till the 20nm process node to introduce 3D transistors, lagging Intel who said yesterday they would introduce the technology at 22nm.
Last year TSMC said it had developed a complete high-performance 22/20nm CMOS logic process using FinFet transistors – which is what Intel calls ‘Tri-Gate’ transistors.
The TSMC 22/20nm process was used to build a 0.1µm2 SRAM memory cell which had 90mV noise at a 0.45V operating voltage.
However TSMC is not moving on Finfets until it feels the design and layout tools are mature - which they are not at the moment.
Intel says the 22nm 3D Tri-Gate transistors deliver up to 37% more performance at the same voltage as its 32nm planar transistors, or use less than half the power while delivering the same performance as 32nm planar transistors.
Over two years ago, IBM, Applied Materials and the College of Nanoscale Science and Engineering (CNSE) of the University at Albany announced an agreement to co-develop Finfet technology for manufacturing 22-nm logic and memory chips.
At that time it was said that Finfets were considered a potential successor to planar transistors for 22-nm chips.
At Europe's leading microelectronics research establishment, Imec, Luc van den Hove, the President of Imec, told us last year: "Around 20nm is when we'll consider 3D devices like Finfets and multi-gate transistors - at 15nm they'll be used for sure."
Apart from FinFets, other exploratory concepts being pursued in transistor design are: Quantum Well devices; Tunnel FET; Graphene FET; and Carbon Nanotubes.
GloFo is a ‘don’t know’ stating: "We and our development partners have longstanding programs to evaluate options for next-generation transistors, including non-planar structures, and we don't see the need for these technologies until beyond the 22/20nm generation."