STMicroelectronics has made a 55nm, 50MHz, CMOS 12-bit ADC which incorporates the LinBIST test structures developed by Edinburgh start-up ATEEDA.
‘The results were found to match or exceed the performance of the conventional test approach, and full characterisation was also achieved using only digital connections to the device,’ says ST and ATEEDA.
Built-in self-test (BIST) is seen as the solution to increased analogue test costs and increasingly difficult access into SoCs. LinBIST is a BIST alternative to high capital cost conventional analogue test equipment.
‘The industry norm for test now exceeds 20% of production costs and can now exceed wafer cost,’ says ATEEDA, ‘highly compressed digital tests have kept ahead of the growth in circuit complexity to control costs, the same cannot yet be said for the analogue circuitry in SoCs. ‘
There’s more functionality on analogue dies but physical access has barely increased and analogue test equipment struggles to match the growth in complexity and need for parallelism.
The analogue circuitry can be small compared to the huge digital blocks on an SoC,’ points out ATEEDA, ‘but factors like the high capital equipment cost, long test time, length of test development and verification, all make the analogue test costs dominant.’
LinBIST is the first pushbutton tool for analogue BIST. Initially focussed on converters, the EDA tool allows users rapidly to customise digital IP (embodied as Verilog) working in synergy with proprietary reference analogue IP.
Together these give a small, completely autonomous BIST block, able to be integrated with the circuit under test.
No Verilog needs to be written manually because the GUI automates the process. It enables selection of the target ADC specification, entry of the test limits, the type of interface required and finally outputs the Verilog for synthesis. The analogue IP is designed to have limited requirements for customisation to any customer target IP.