Xilinx and Thales will demonstrate a partially reconfigurable FPGA-based single chip architecture for military radios at the Software Defined Radio Technical Conference (SDR'07).
The demonstration will implement multiple applications in an FPGA using partial reconfiguration.
“Single chip partially-reconfigurable FPGA architecture is a major step to achieve an efficient solution for software-defined radio applications because it provides the flexibility required to support and deploy different and multiple waveforms," said Cedric Demeure, Thales technical business unit director.
Partial reconfiguration adapts a hardware design to modify applications while keeping the rest of the device active. By enabling partial reconfiguration, the FPGA can support more than one application in a smaller device providing that the applications are mutually exclusive.
Xilinx also offers its Virtex-4 FX FPGA-based Joint Tactical Radio System (JTRS) software defined radio development kit to build similar systems.
“The kit enables developers to investigate alternative design approaches to lower the cost and power of their SDR modem with low risk and relatively low cost,” said Manuel Uhm, senior DSP marketing manager at Xilinx.