Avago Technologies has a 25Gbit/s serialiser/deserialiser (serdes) core in 28nm process technology has demonstrated compliance with the Common Electrical Interface (CEI) standard for 25G Long Reach (LR).
Achieving CEI-25G-LR compliance it is intended for Asic design in data networking applications and supports the push for 100G Ethernet infrastructure.
Avago demonstrated its 25G SerDes cores in backplane applications at the DesignCon 2012 exhibition in the Santa Clara Convention Center in SantaClara, California from January 31 to February 1.
The demonstrations showed the Avago 25G SerDes running on over 30-inch PC board traces.
“This compliance is not only another first for our SerDes cores, but it marks a significant step forward in the march to 100G Ethernet Infrastructure,” said Frank Ostojic, v-p and general manager of Asic products at Avago.
“As part of the push toward 100G, Avago is planning to use our 25G SerDes as the basis for future standard products. Capable of driving 5 meters of copper cabling at low power, the 25G SerDes is suitable for a range of applications and is now available to a larger group of customers,” said Ostojic.
The 28nm Avago SerDes cores feature a decision feedback equalisation architecture, which can reduce overall power, while maintaining data latency and jitter and crosstalk tolerance.
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