RF Engines claims to have simplified digital filter design with
an FPGA-based architecture which can be used to perform up-sampling
or down-sampling of high speed signals.
The technique, called fractional resampling, is a signal
processing function that enables the manipulation of the signal
sample rate, so it can be matched to the requirements of the
system.
“The aim is to provide designers with greater freedom in
their system design and to a shortened timescale,” said John
Summers, RF Engines’ v-p of sales and marketing.
Summers said he expects the filter design to be used for
matching symbol and sample rates in digital receivers. “This
will simplify telecoms modulators and demodulators,” said
Summers.
The firm is offering the filter core IP as an EDIF netlist for
either Xilinx or Altera FPGA devices which is custom generated for
each requirement.
An example core is able to down-sample 512 channels
simultaneously and independently.
www.rfel.com