Wally Rhines, CEO of Mentor Graphics, reckons the semiconductor industry is on a learning curve that will result in ICs with 40 billion transistors by 2018.
The question he asks is: how will design tools be capable of producing 40 billion transistor devices?
With the adoption cycle for most tools being about eight years, Rhines asks what are the tools we have today that will support 40 billion transistor designs in eight years’ time?
System-level design will become a necessity.
“We must raise the level of design abstraction from RTL to transaction-based design,” says Rhines. “I think we are about due for that transition.”
These highly complex chips will require a dramatic increase in the speed of the functional verification process. “We must achieve a x1,000 increase in verification,” he says.
“We will achieve this through the use of mixed-mode simulation and we must stop doing redundant verification. But the big change will come when we use transactional testbenches for emulation. This can be 500 to 1,000 times faster than software simulation.
“So, given these technologies, it will probably not be a problem getting there.”
In the area of physical design, Rhines expects a similar change, with greater parallel-optimisation of the place and route process. This is a process Rhines calls multi-corner, multi-mode physical verification, where corners refer to the operating conditions of the chip.
The other factor Rhines highlights is the dramatic increase in the cost of software design with these 40 billion transistor chips.
“The hardware design cost of a chip has not increased in the last decade, but the same is not true for the software cost,” he says. “The software design cost has been increasing dramatically.”
To meet the challenge of rising software costs, Rhines says there is a need to change design methodologies. He identifies three software design techniques that will have an impact of the cost of chip design projects – software IP re-use, embedded software automation process such as Autosar for executable UML, and the growing use of open standards such as Linux.
Last year, Mentor bought Embedded Ally, a California-based provider of Linux, middleware and software for mobile and embedded devices. “This has pushed us into the open source community,” says Rhines.
“We know that software is the most serious part of the cost equation for chip development.”
Mentor’s CEO is irresistibly upbeat about the immediate prospects for the design tool industry. “The EDA industry is red-hot right now,” he says.
According to Rhines, the EDA industry is following the semiconductor market out of recession, with opportunities for growth this year. “We are in a very strong bounce back. I expect Mentor Graphics to show 8% growth this year,” he says.
The chip design tool industry draws its strength from the semiconductor market, which is forecast to bounce back with 25% growth or
better his year.
“The EDA industry normally lags the semiconductor industry,” says Rhines. “This is normally because revenues must grow back some before companies start reinvesting in R&D.”
“Eight per cent is not stunning, but it’s OK,” says Rhines.
See: EDA firms get silicon IP strategies in place