STMicroelectronics and the Microsystems Technology Laboratories (MTL) of Massachusetts Institute of Technology have presented the results of research for low-power microprocessor technology at this year’s European Solid-State Circuits Conference in Helsinki, Finland.
Implemented in ST’s 65nm CMOS process, the ST-MIT designed voltage-scalable 32-bit microprocessor system-on-chip device reduces power consumption to 10.2pJ/cycle at 0.54V, while the SRAM memory cells can operate at 0.4V.
Memory-access power consumption is further reduced through the use of a small latch-based instruction and data caches at the first level of the hierarchy.
"MIT researchers and STMicroelectronics engineers worked together to develop and implement a number of architectural and circuit techniques to reduce power consumption," said Prof. Anantha Chandrakasan, department head of EECS at MIT.
The energy-efficient processor is expected to be used in sensor network applications such as embedded bio-medical systems.
“This breakthrough technology can enable the development of an entirely new generation of microprocessors for wireless sensors and implantable medical devices,” said Alessandro Cremonesi, advanced system technology general manager at STMicroelectronics.
"Our work with MIT aspires to play a key role in expanding the industry’s horizons in ultra-low-power technologies,” said Cremonesi.
The device also has on-chip low power clock generation and analogue-to-digital conversion, as well as a set of peripherals, such as timers and serial interfaces able to work at the minimum voltage supply.
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