Scaling is no longer delivering sufficient cost reduction and there’s not much hope of getting back to traditional Moore’s Law cost decreases purely by process technology advances, according to Joe Sawicki, vp and gm of the design to silicon division at Mentor Graphics speaking to the IEF 2011 meeting in Seville this morning.
Most of the IC learning curve cost reduction has been driven by scaling which has reduced the cost of a $10 function in 1994 to 4 cents today.
However double patterning makes it difficult to keep the increase in wafer cost below 15% per node at 20nm and 15nm.
90nm delivered a 60% reduction in the cost of a gate, said Sawicki, 65nm delivered a 12% drop in cost, 45nm delivered a 9% drop in cost, 32nm delivered a 3% drop in cost and, at 22nm, the cost of a gate actually increases.
There is no likely improvement in silicon area/hour/capital dollar for next generation lithography, he said.
Advanced Mask Optimization for process and stacked die for packaging were the routes he proposed for keeping the industry on the cost reduction learning curve.
"The semiconductor learning curve will continue long after Moore’s Law is dead," said Sawicki.