Samsung Electronics’ foundry business has collaborated with Cadence to develop a design-for-manufacturing (DFM) infrastructure.
This involves the development of “in-design” and signoff DFM flows to tackle physical signoff and electrical variability optimisation for 32-, 28- and 20nm system-on-chip (SoC) designs.
According to the firms, the intention is to address both random and systematic yield issues with a foundry option for advanced-node designs built on the Cadence Encounter digital and Cadence Virtuoso custom/analog implementation solutions.
“As we expand our customer base at advanced process nodes, customers require various design flows,” said Kyu-Myung Choi, senior vice president of Infrastructure Design Center, Samsung Electronics.
“By teaming with Cadence to build a strong foundry ecosystem for advanced node designs, we’ve achieved numerous benefits we can pass along to our customers such as reducing risk and speeding time to market," said Kyu-Myung.
As semiconductor manufacturing complexity increases at the 32- and 28nm process nodes there is an impact on design cycle time and time to yield compared to previous nodes.
Samsung Foundry said it can use the hierarchical design approach and pattern matching to perform effective and accurate systematic failure analysis.
"We’ve enjoyed great success at 32 and 28 nanometers with Cadence, and we have now extended our advanced DFM flow to 20 nanometers as well,” said Kyu-Myung.
The DFM flows developed at Samsung Foundry use technologies such as Cadence Pattern Classification technology which allows it to classify the yield detractor patterns into practical pattern libraries.
The infrastructure enables Samsung Foundry’s customers to leverage the in-design and signoff pattern matching with automated fixing flows in Encounter and Virtuoso. .
“We worked closely with Samsung Foundry to integrate our robust DFM suite, which continues to gain momentum as the advantages of in-design DFM become increasingly evident,” said Tom Beckley, senior vice president, Custom IC and Signoff, Silicon Realization Group at Cadence.
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