Ceva’s latest DSP core for embedding in system-on-ship devices for comms and wireless applications will run at 1GHz using standard 40nm process technology.
The CEVA-X1643 is the latest in a range of IP cores which are being licensed by OEMs for embedding in devices such as smartphones and surveillance systems.
According to Eran Briman, v-p of marketing at CEVA: “The DSP’s advanced data cache architecture and software development environment dramatically simplifies the migration of legacy code to the CEVA-X architecture, enabling true, all-in-C programming of the CEVA-X1643.”
See also: Why Intel bought Infineon's mobile chip business
The CEVA-X1643 DSP features a Very Long Instruction Word (VLIW) architecture combined with Single Instruction Multiple Data (SIMD) capabilities.
Its 32-bit programming model will process up to eight instructions per cycle, and 16 SIMD operations per cycle.
A tightly-coupled memory architecture should simplify RTOS design and multi-tasking.
There is also support for seamless migration from TI C6x C-code.
There is configurable AXI bus width, parallel read and write transactions, read after write transactions.