MIPS Technologies has worked with semicondcutor production services company eSilicon on the tapeout of a multi-processor MIPS32 cluster on the low-power 28nm SLP process technology at foundry Globalfoundries.
Wafers are running in the foundry's Fab 1 in Dresden, Germany, with silicon expected in early 2012.
MIPS provided the RTL based on its MIPS32 1074Kf embedded multi-processor technology and eSilicon performed the synthesis and timing-driven layout of a three microprocessor cluster running at 1GHz.
The 1074Kf CPS is based on a MIPS32 74K processor core.
“We worked closely with eSilicon on this project to not only demonstrate the capabilities of the high-performance 1074K CPS in a new low-power process, but also to enable our customers to use the resulting implementation in their SoC designs,” said Gideon Intrater, v-p of product marketing and applications, MIPS Technologies.
To reach the 1GHz target without compromising low power, eSilicon’s custom memory team created custom fast cache instances (FCIs) for the L1 caches to replace standard memories that were in the critical path of the design.
“Our custom FCIs did the trick in enabling us to meet the fast-approaching shuttle date. Together with the high quality of the MIPS 1074K design, we were able to quickly meet the challenging performance targets in a low-power process,” said Paul Hollingworth, eSilicon VP of strategic marketing.
www.esilicon.com