A Purdue University-led team decided to try to find out just how far current scaling techniques will stretched, and reached 5nm.
Through atomistic simulations, they looked at several promising device designs and material combinations: carbon nanotubes, graphene nanoribbons, and III-V and silicon ultra-thin-body devices and nanowires.
They performed numerical simulations of intrinsic characteristics, limiting factors and design impacts.
The simulations show that:
With careful engineering, good sub-threshold swing can be obtained for many of these device alternatives for gate lengths down to 8 nm.
Non-planar devices can provide good performance even at 5nm gate lengths.
When the bandgaps are the same, carbon nanotube FETs and small-diameter silicon and III-V nanowires exhibit roughly the same performance, but the details of the potential profile and the onset of interband tunneling are critical.
"While the work is not intended to be definitive, it does serve as a guide to avenues of future research," said the IEEE.
The diagrams below show different idealised n-type FETs with 5nm gate-length:
3-D structures including gate-all-around single-wall carbon nanotubes with 63-nm diameters and Ω-gated nanowires the (gate covers 75% of the nanowire perimeter) made of strained silicon.
Single- and double-gate armchair graphene nanoribbon.
Double-gate silicon ultra-thin-body devices.
IEDM paper 11.2
Ultimate device scaling: Intrinsic performance comparisons of carbon-based, InGaAs and Si field-effect transistors for 5-nm gate length.