IBM researchers have integrated high-performance graphene FETs and RF passives into a 200mm wafer-scale CMOS-compatible fabrication processing.
"A major obstacle with graphene is the difficulty of building a gate dielectric (insulating layer) on its inherently inert surface," said the IEEE. "Fortunately, graphene layers grown by controlled vapor deposition (CVD) can be transferred to many types of substrates."
To take advantage of this property, the team built silicon wafers containing pre-defined embedded gate structures, and then transferred CVD-fabricated graphene layers onto them.
The proof-of-concept circuit is a frequency doubler, which demonstrated a conversion gain of around -25dB at an output frequency of 2GHz.
"This performance was nearly constant from 25-200°C, indicating that both n- and p-transconductance are temperature-independent in this range, a new finding for CVD graphene-based devices," said the IEEE.
Except for the CVD graphene transfer, all processing was done in a conventional 200nm fab.
The single image below is a cross-section of the post-CMP wafer showing the inverted-T gate structure.
The four images show:
(a) an 200mm graphene FET wafer
(b) single die
(c) A typical fully processed device
(d) an enlarged view of the device showing the embedded gate structure with two-finger design
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IEDM paper 2.2:
Graphene technology with inverted-T gate and RF passives on 200mm platform.