Lattice Semiconductor has released two new families of 90nm FPGAs. The LatticeSC ‘system chips’ are high-end parts intended to compete with Xilinx’s Virtex-4 and Altera’s Stratix II devices.
The LatticeECP2 chips are low-cost FPGAs targeted at the Spartan-3/Cyclone II market.
“The SC is our first entry in a while in the high density FPGA market,” said Shakeel Peera, strategic marketing manager at Lattice.
Peera used the example application of a line card in which functions including datapath, memory control, control plane bus, traffic manager and backplane driver all had to be connected.
These requirements have led the firm to provide between four and 32 Serdes channels (supporting data rates from 600Mbit/s to 3.4Gbit/s); up to 900 pins of ‘Purespeed’ parallel I/O (around half of which could be used to give 2Gbit/s LVDS signalling); and eight programmable PLLs and 12 DLLS per device.
Jitter in the Serdes channels is low enough to enable them to drive across up to 60in. of FR4, and the five members of the SC family offer an FPGA fabric of between 15,000 and 115,000 four-input LUTs running at 500MHz. Operating voltage is 1.2V, but can be reduced to 1.0V for low-power applications.
An interesting feature is the inclusion of between four and 12 blocks of 50,000 Asic gates. Lattice calls these MACO (masked array for cost optimisation) blocks, and implements DDR2 memory controllers, Gigabit Ethernet cores via a ‘FlexiMAC’ multiprotocol engine, and an SPI4.2 core.
“We intend to use these as a way of delivering hard IP to our customers,” said Stan Kopec, corporate v-p of marketing. Lattice said that hard IP implementations of these functions can be achieved in 1/10th the area of a soft version, at lower power and with better performance.
The low-cost ECP2 devices are a migration of the existing 130nm ECP parts to a 90nm process.
The move doubles the LUT density, halves the part cost, and increases I/O speed by 50 per cent, according to Lattice. The company has also added support for DDR2 and included a DSP block.
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