Toshiba is showing a low-voltage SRAM technology at the ISSCC this week which reduces memory cell failure rate by four orders of magnitude at 0.7V, so overcoming the main challenge in achieving practical, low voltage SRAM.
The circuit design can be applied to the memory compiler, software that automatically configures SRAM, contributing to shorter design lead times and bringing an effective solution to SOC development. .
An SOC's active power consumption is proportional to the square of the supply voltage. For instance, if supply voltage were reduced from 1.0V to 0.7V (by 30%), power consumption is decreased by approximately 50%.
Voltage scaling of SOCs has been a challenge, because embedded SRAM loses stability in the memory function at low voltage. The memory cell transistors of SRAM are smaller than those of other logic circuits, which makes SRAM operation susceptible to transistor variability at low voltage (2).
Since the threshold voltage of smaller transistors experiences greater variability, an SRAM cell integrating small transistors is subject to large variations in operating characteristics, particularly in low voltage operation.
Toshiba has overcome this problem with a new method that employs read-assist and write-assist techniques and secures the function of a low voltage SRAM.
Read-assist and write-assist techniques are recognised as a means to stabilize SRAM functionality by optimizing bit-line and word-line level during read and write operation. However, the conventional write-assist technique requires adjustment in circuit parameters of the SRAM's negative voltage generator to match the SRAM capacity. This has been an obstacle to design efficiency and has hindered practical application.
Toshiba's solution employs a newly developed negative voltage generator with bit-line-capacitance replica, which adaptively optimises the negative level to the SRAM capacity. This approach eliminates the burden of adjusting circuit parameters in accordance with the SRAM configuration by automating the SRAM design process.
A test chip fabricated with 32nm high-k/metal gate process technology cut voltage for stable operation from the 1V typical for conventional SRAM to 0.7V. Equally as significant, the failure rate decreased by four orders of magnitude, i.e. a 10,000 times improvement.
Other approaches proposed for securing SRAM stability employ a memory cell that increases the transistor count from the typical number of six. However, Toshiba reckons its approach is more efficient, as it requires no increase in transistors, avoiding the penalty of an increase in the SRAM cell area.
Cutting-edge SOCs are designed to use a supply voltage around 1V. However, further reductions in set power consumption require much lower voltages.
Figure 1 - Impact on cell failure rates
Figure 2 - Circuit configuration of new technique
