HDL heroes"Transistor counts double every 18 months," according to Gordon Moore and that means there are some hefty FPGAs with up to 100,000 usable gates. Old design techniques are struggling top cope. Roy Rubenstein reports on how the use of HDLs profit the FPGA designer While they differ in their insights, all the tool vendors agree on the underlying reason for the trend: FPGA designers are increasingly adopting hardware description languages (HDLs) thanks to Gordon Moore's famous law.
As Tim Colleran, Synopsys' director of FPGAs points out: "With the advent of 0.35 and 0.25?m processes, there are now some pretty big FPGAs with 50,000 and 100,000 usable gates." The result is that FPGA users are having to grapple with increasingly complex designs and are finding that traditional design techniques are no longer adequate.
Roland Mattison, director of programmable product solutions at Viewlogic, agrees. "With FPGAs getting larger, the traditional method of schematic capture [for design entry] takes longer to do." Schematic capture involves selecting logic blocks such as flip-flops and gates and linking them on-screen. Accordingly, entering a 10,000 gate design is a laborious undertaking.
The benefit of using a HDL such as Verilog or VHDL is that an engineer can enter a design using a higher level of representation. For example, an adder is generated simply by using the "+" operator in VHDL. "A few lines of code can represent what would otherwise be described in multiple pages of schematic," said Andy Haines, v-p of marketing at Synplicity, a US EDA company concentrating on tools for FPGA design.
Mattison highlights another reason why FPGA designers profit from the use of HDL. "FPGA designers are typically involved in system design. They have a larger set of issues to deal with and have less time to learn about the idiosyncrasies of a particular architecture," he said.
This is perhaps the most important advantage of HDLs: how a design is manipulated once encapsulated in HDL code. Synthesis tools take the code and produce a netlist output, used by the place-and-route tool to map the design onto the FPGA or complex PLD.
Using synthesis, the user can dictate timing constraints that must be met or can define the extent of the device area - the logic resources - the design can have. Such optimisation using a schematic capture is simply beyond all but the most skilled of designers requiring hours of effort compared to the minutes needed to run the synthesis tool.
It is these advantages which have led to the recent rapid uptake of HDLs by programmable logic users. According to Haines the overall market penetration of HDLs among FPGA and complex PLD designers is 25 per cent. "By the year 2000 it will be 90 per cent," he said.
Moreover, interest in the tools is not confined to traditional FPGA users. Asic designers - those HDL trailblazers - are adopting FPGAs to implement their previous low end gate array designs. They expect nothing less than to use the same sophisticated tools and techniques they employ for their Asic designs.
Tools and issues
There are several issues to be considered when choosing HDL tools for FPGA design. One is how integrated the tool environment is. Viewlogic makes great play of its intelliFlow tool which offers the engineer a single, integrated design environment - from HDL entry to simulating the final design. Another is the quality of the synthesis tool: how easy is it to use, and whether it makes best use of an FPGA's underlying architecture. This not only includes exploiting the device's logic cells but also the quality of information the synthesis tool passes to the place-and-route tool.
Synplicity's Haines points out that its synthesis tool looks for optimisations at two levels: when compiling the RTL code and when translating a design to a particular logic device. "We start optimising much earlier." Synplicity also offers HDL Analyst which allows viewing, the RTL as well as the gate level, of the synthesis tool's results. This helps an engineer identify (and modify) critical parts of the design.
Mentor Graphics offerings include the Renoir graphical entry tool, enabling a design to be captured without being fully conversant in HDL, and two synthesis tools: Galileo and Leonardo. Galileo is a push-button synthesis tool, taking an existing netlist or RTL code to produced the synthesised netlist. Leonardo has a more sophisticated interface with a flow manager to control the trade-off between timing and area constraints. Meanwhile, Synopsys' FPGA Express caters for FPGA designers who want to implement a design quickly, through to experienced HDL users, such as Asic designers. "Used in simple push button mode and synthesising with placed constraints can make a big difference on the information passed to the place and route tool," said Colleran. For a particular 25,000 gate design, a 20 per cent improvement in performance was achieved: "This corresponds to a speed grade or two, and can have a huge impact on overall cost."
The legacy problem Maintaining designs over a 50 year period can be somewhat tricky. It is a problem a design team at GEC Marine VSEL is grappling with: maintaining equipment that has parts that are no longer available. GEC Marine VSEL's approach is to capture the existing design in VHDL and implement it with the use of FPGAs. "Once you've got a VHDL description of the board, it can be easily maintained even after a device has become obsolete," said Stephen Postlethwaite, an electronics design engineer on the team.
To this aim, Postlethwaite went on the Esperan course to learn VHDL. "It was a useful course on a complicated topic; you?re writing software but with the hardware is mind." Tackling the board design problem has proved far more taxing than any of the exercises undertaken on the course.
Three months later and Postlethwaite is a firm believer in the benefits of VHDL. The ability to simulate the hardware, a facility not available using schematic capture, means "you are far more confident it will work first time".
His one note of caution: don't underestimate the amount of learning required when embracing HDLs.
Training for HDLs Training companies Esperan and Doulos certainly confirm the second wave of interest in hardware description languages from the FPGA community. "There has been a major growth in interest [in learning HDLs] in the last two years," said Antony Dennis, an Esperan director. Robert Hurley, Doulos' business manager, has seen a 30 per cent increase in course attendees in the last year.
The reasons for the increased interest include the greater complexity of programmable logic devices; a general recognition of the benefits of HDLs as a design methodology which, being independent of tools and technology, aids design reuse; and the increasing prevalence of PC-based synthesis tools.
Esperan offers five-day courses on HDLs split between lectures and hands-on design. The lectures cover language syntax and design methodologies in equal measure. The company also offers a multimedia training course which covers material corresponding to half of the five-day course. Doulos offers standard and advanced training courses. Its standard five-day course takes an engineer from "scratch to project readiness", with attendees being trained on whichever set of tools they will be using on their project.
Further information Tools www.synplicity.com
www.synopsys.com
www.viewlogic.com
www.mentorg.com
Training www.esperan.com
www.doulos.co.uk