Editor's choice of 10 programmable devices which are intended to move configurable system design to a new level of performance.
Achronix Speedster SPD60 is a 1.5GHz asynchronous FPGA which includes 10.3Gbit/s serialiser/deserialisers (serdes).
Within each device the repeating logic block has eight four-input look-up tables, storage elements and 128 bits of RAM. These logic blocks are surrounded by interconnect and asynchronous data routing blocks.
The chip supports memory interface speeds of up to 1.066Gbit/s.
www.achronix.com
Actel’s nano versions of its Igloo FPGAs are characterised by their
sub-$1 price tag as much as their power and performance specifications.
Power consumption is as low as 2µW and package size 3x3mm.
The Igloo nano FPGAs range in densities from 10k to 250k system gates.
The devices support 1.2V to 1.5V core and I/O operation. I/O features include hot-swapping and Schmitt trigger inputs.
www.actel.com
Altera Stratix IV GT and Arria II GX 40nm FPGAs feature transceiver speeds from 155Mbit/s to 11.3Gbit/s.
Stratix IV GT has 24 transceivers operating at 11.3Gbit/s, and up to 530K LEs, 20.3Mbit internal RAM and 1,288 18 x 18 multipliers.
Arria II GX devices are for lower-power applications using protocols such as PCI Express and Gigabit Ethernet. They feature up to 16 3.75Gbit/s transceivers, 256K LEs, and 8.5Mbit of internal RAM.
www.altera.com
Atmel’s AT91CAP7L customisable ARM7 microcontroller is intended for 12-week design turnarounds.
It has 200k gates of metal programmable cell fabric that can be used to implement customer IP, hardware accelerators, additional processor cores, or other peripherals in a classic SoC configuration.
According to Atmel, NRE charges are $75,000 and unit costs are as low as $5, without requiring a separate ARM licence.
www.atmel.com
Cypress Semiconductor’s programmable system-on-chip (PSoC) family has moved in to its second generation.
A major redesign from the first generation PSoC, the programmable element now has the look of a PLD, with 20k density. The on-chip analogue circuits, which are also configurable, have been given 20-bit resolution. Most significantly, Cypress has replaced its proprietary 8-bit processor core with an 8051-core in the 8-bit devices and an ARM Cortex-M3 processor in the 32-bit chips.
www.cypress.com
Lattice Semiconductor’s ECP3 mid-range FPGA family features a DSP capacity of 320 18x18 multipliers, 6.8Mbit of memory and up to sixteen 3.2Gbit/s serdes channels.
There are five devices that offer standards-compliant multi-protocol 3G serdes, DDR1/2/3 memory interfaces and cascadable DSP slices.
Toggling at 1Gbit/s, the LatticeECP3 FPGAs also feature LVDS I/O as well as embedded memory of up to 6.8Mbit.
Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O.
www.latticesemi.com
Lime Microsystems’ LMS6002 is a multi-band multi-standard RF transceiver IC designed for femtocells and small wireless basestations.
The transceiver operates at user-selectable frequencies between 375MHz and 4GHz. It can be digitally configured with 16 user-selectable bandwidths of up to 28MHz.
It is programmed via a standard Serial Port Interface (SPI) and is packaged in a 9x9mm 116-pin DQFN package.
www.limemicro.com
SiliconBlue Technologies has designed a range of low-power SRAM-based FPGAs based around the traditional four-input look-up table (LUT) logic cell. Essentially, it is a 16-bit RAM with a register on its output which can be bypassed.
The first product, iCE65L04, has 4,000 logic cells. Its core consumes under 25µA running at 32.768kHz, and benchmarking at 32MHz.
The company has recently introduced a high-speed version with a 65% speed boost due to process optimisation.
www.siliconbluetech.com
Xilinx Virtex 6 and Spartan 6 differ from previous generations of the firm’s FPGAs in that they are also being offered in application specific reference designs.
Using 40nm for Virtex 6 and 45nm for Spartan 6, the FPGAs use voltage scaling to cut power consumption by up to 50% compared with previous generations.
There are up to 760k logic elements, more than 38Mbit of BlockRAM and 2,000 DSP slices available.
Four I/O 64 transceivers run up to 11.2Gbit/s and there are PCI Express-compliant hard blocks and dedicated DDR3 memory controllers.
www.xilinx.com
Xmos Semiconductor L series is the UK-based start-up’s multi-threaded configurable processor.
A single core version, the XS1-L1, which is made on a 65nm process, will run eight threads, it performs 400MIPS and has 64kbyte of SRAM. Power consumption is under 500µA in sleep mode and 15mA in standby.
A dual-core version, the XS1-L2, will run 16 threads.
www.xmos.com