Traditionally, digital logic met designers’ needs for low static power, but this has changed as process nodes have shrunk. Leakage current is now the primary challenge for FPGAs as process geometries decrease.
Power consumption becomes a critical issue as static power increases dramatically at the 65nm and below process node. Static power consumption rises largely because of increases in various sources of leakage current.
Dynamic and static power
Power consumption is composed of static and dynamic power. Static power is the power consumed within an FPGA when it is programmed with a programmer object file (.pof), with no clocks operating. Both digital and analogue logic consume static power. In an analogue system, static power is primarily composed of the quiescent current of the analogue circuit based on its interface configuration.
Dynamic power is the additional power consumed through the operation of the device caused by signals toggling and capacitive loads charging and discharging.
The main variables affecting dynamic power are capacitance charging, the supply voltage, and the clock frequency. Dynamic power decreases with Moore’s Law due to the process node shrinks which reduce capacitance and voltage.
The challenge increases when more circuits are implemented with each process shrink and the maximum clock frequency increases. While the power reduction declines for an equivalent circuit from process node to process node, the FPGA capacity keeps doubling and the maximum clock frequency keeps increasing.
Low power, high performance
The capability to control and program power settings is an unprecedented technique for reducing power in high-end FPGAs. Traditionally, high-performance FPGAs are implemented with a high-performance fabric where every logic element (LE) provides the maximum performance with a subsequent high leakage power
Programming power settings enable the logic fabric of an FPGA to be programmed at the logic array block (LAB) level by providing high-speed logic or low-power logic, depending on which is required by the specific logic path. By doing this, the small percentage of circuits that are timing-critical are “selectable” to a high-speed setting, with the remainder using a low-power setting, this can result in a 70% decrease in leakage power for the low-power logic.
By placing unused logic, as well as digital signal processing (DSP) blocks and memory into the low-power modes, power can be further decreased. Being able to program power settings enable an optimal combination of high-speed logic to achieve the desired system performance while the remainder of the logic can be placed into low-power mode, thereby minimising leakage current and resulting in the lowest power consumption.
Delivering the exact amount of high speed logic requires a design to reach its desired performance while being controlled with a very high degree of precision. The programmability between high-speed and low-power logic is controlled on a per-tile basis (each tile containing two LABs, or a LAB and DSP block, or a memory block, all with associated routing). Controlling individual tiles as either high-speed or low-power on large FPGAs can achieve the lowest possible power for design development software. This includes specifying timing constraints to optimise the design when placing tiles into high speed or low power mode automatically.
Core voltage
Selecting the core voltage (0.9V or 1.1V) of the FPGA allows designers to maximise performance requirements of the design. A 0.9V core voltage can provide an overall minimum dynamic and leakage power, while a 1.-V core voltage can deliver the overall highest performance.
Dynamic power scales with the square of core voltage while static power scales by the power of 2.5 of core voltage. Selecting core voltage input supplies all LABs, memories, and DSP functions in the core fabric, thus affecting fabric performance. When choosing a core voltage to use, a designer must take into account the system performance requirements reported from the timing analysis.
When combining the ability to program power settings and select core voltage, various performance and power operating points could realise a power reduction of over 50% at 1.1V. The combined static and dynamic power varies across combinations of core voltage and percentage of high-speed versus low-power logic.
An FPGA logic architecture and interconnect fabric can deliver high efficiency and performance. Utilising this architectural combination can allow more logic to be packed with less routing, thus increasing performance and reducing power.
Interconnect architecture
Furthermore, FPGAs utilising interconnect architecture can maximise performance, minimise congestion, and minimise power. Interconnects provide the connectivity between different LABs and can be measured by the number of “hops” required to get from one LAB to another. Adding interconnect hops increases capacitance, the fewer the hops, the less high-speed logic required to meet performance.
Design implementation details can improve performance, minimise area, and reduce power. Historically, the performance and area trade-offs have been automated within the register transfer level (RTL) through the place-and-route design flow.
Bringing power optimisation into the design flow of area-optimised designs can enable power reductions of 10% to 40% over standard performance. Software optimisation tools automatically use the FPGA architecture capabilities to further reduce power.
As the progression to very small process nodes – 65nm and below – delivers the expected Moore’s Law benefits of increased density and performance, the performance increases will result in significant increases in power consumption. If power-reduction strategies are not employed, static power consumption will increase to critical levels.
Paul Ekas works for Altera