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The requirements of flash memory scaling are driving the process technology of the semiconductor industry with the NAND flash industry demanding a doubling of density every year, according to Luc Van den Hove, COO of IMEC, speaking to the International Electronics Forum 2008 in Dubai, this morning.
The workhorse manufacturing technology for 32nm, and early entrants to 22nm will be double patterning rather than EUV, according to Van den Hove.
“The feasibility for EUV is demonstrated”, said Van den Hove, “but there are many challenges out there before it becomes suitable for manufacturing, and it will take a few years before we’re at that stage.”
Asked what he thought about Intel’s announcement that it would not be using EUV at 22nm, Van den Hove replied: “Intel recently announced it would not be using EUV for 22nm technology in 2010. I agree with that. EUV will not be ready until 2012/2013.”
Van den Hove added: “The requirements for various application segments are different. We can be talking about pitch, not line width. Flash needs a very tight pitch; logic needs a more relaxed pitch.”
Van den Hove saw two current challenges: materials and packaging. “We have to learn how to handle the new materials, like high-K, and the big thing now is 3-D, stacking chips”, he said, “there are many drivers. Integration density using 3-D allows the use of more transistors; if it is done well, the shorter interconnect can increase performance; and you can integrate RF, sensors and batteries with logic, SRAM and flash.”
Asked if there was anything in the offing to get over the low-power issues, Van den Hove replied: “High-K is absolutely needed and FinFETs are needed if we are to dissipate the heat.”
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