Altera's first 65 nanometre FPGAs will not sample until the third quarter of 2007, despite the launch today of design software for the devices.
Giving further details of its Stratix III family, the programmable logic firm said the date for samples is in line with designers expectations of needing first silicon, with production planned for Q1 2008.
Meanwhile, rival Xilinx started shipping samples of its 65nm Virtex-5 devices in May of 2006.
With Stratix III, the shift from 90nm to 65nm has allowed Altera to double transistor counts, and the largest member of the Stratix III family will contain some 338k logic elements and 17.2Mbit of memory.
However, most of Altera's design effort seems to have gone into power, with the aim of reducing it wherever possible.
"Power is an important challenge at 65nm," said Danny Biran, v-p of corporate marketing at Altera.
"If you double density you increase power consumption by a factor of two as well, and you get more leakage, so higher static power consumption, and performance enhancement leads to more dynamic power consumption."
However, to keep within existing power budgets, overall consumption must stay the same, and Altera has addressed this with a new scheme for selectively lowering power across the logic elements of the devices.
The Quartus-II software that fits designs to the FPGA can identify the critical path through a design. Logic on this path is run at full speed and voltage, while the remaining logic runs at a lower speed and voltage to minimise power consumption.
"In the past there was no granularity at the block level," said Biran.
A test of 71 customer designs showed that on average just 20 per cent of the design was required to run at the full speed and power.
At a more coarse level, the user can also choose to run the core logic at either 0.9V or 1.1V. At the lower voltage, Altera claims dynamic power is 55 per cent less than the Stratix II devices, while static power is down by 60 per cent. At 1.1V, the figures are 33 per cent for dynamic power and 46 per cent for static.
These numbers imply that running Stratix III at 1.1V rather than 0.9V raises dynamic power by 50 per cent and static power by 35 per cent. The dynamic power figure is in line with a simple CV²f calculation.
On the performance side of things, DSP speed has been increased from 370MHz in Stratix II to 550MHz - the same quoted speed as Xilinx's Virtex-5 parts.
Memory interfaces have also been expanded and speeded up. At the fast end, the devices will support DDR3 and QDRII+ at 400MHz. I/O in the form of LVDS has been moved to 1.25Gbit/s, up from 1Gbit/s.
Altera is planning four versions of Stratix III: The standard part, enhanced devices with more DSP and memory, GX devices with high speed serial interfaces, and HardCopy, the firm's structured Asic replacement.
Stratix III is using TSMC's 65nm process with strained silicon and triple oxide transistors.
Altera