Overcoming fixed-performance limitations can introduce multiple levels of hierarchy and complexity. Stéphane Monboisset, processing platforms product manager at Xilinx, believes the FPGA firm's latest extensible processing platform delivers the flexibility and productivity needed to meet design-to-market pressures.
Embedded processors form the heart of most embedded systems and general purpose processors are able to provide the fundamental capabilities needed by many vertical sectors.
The use of application-specific devices is still common, however, and they are often enabled by the same core architectures. Typically today that core architecture is likely to be ARM-based, as it is arguably the most widely deployed of all third party IP, even amongst integrated device manufacturers who have their own legacy processor technologies.
General purpose processors and other application-specific standard parts (ASSPs) come in many forms but share a common feature; their fixed design delivers a defined level of performance. Extending that performance is difficult in a general purpose device, ASSP or, particularly, in a fully developed ASIC.
The introduction of the extensible processing platform, therefore, represents a significant development in the embedded space; providing a system-on-chip platform that can be tuned by system engineers to increase performance or the execution of critical functions, while incurring minimal additional engineering cost, without increasing system complexity or impacting on time-to-market.
Meeting demand while managing complexity
Demand for more performance is responsible for the trend towards multicore processing and this has, in turn, created greater design complexity. Multicore processors feature strongly in today’s embedded systems, but many applications now require multiple multicore processor-enabled devices, as demand for more performance requires more powerful devices or multiple integrated devices. This in turn has increased system hierarchy and introduced greater design complexity at the system level.
Managing that hierarchy and its inherent complexity significantly lengthens development cycles, an aspect of today’s design environment that increasingly directly opposes market demand for more frequent feature enhancements or product introductions. Current solutions to combating market pressure essentially involve an exercise in risk management; ASSPs offer a faster time to market than an ASIC, but they also deliver a fixed level of performance and reduced opportunity for differentiation.
Even if the performance requirements remain constant, the risk management still involves deciding how much differentiation is needed, if financial and time budget constraints allow then an ASIC may be the best route, but if they don’t then it may feel like the only appropriate option is to choose an ASSP.
For many years, FPGAs have offered an alternative to both ASICs and ASSPs, as they are faster to design than an ASIC and offer more flexibility than an ASSP.
However, in some applications the compromise comes in the form of performance and power consumption, both of which may be less compelling than an ASIC/ASSP alternative. FPGA vendors continually make steps towards improving the power consumption and performance of their FPGAs but occasionally an opportunity arises to take a technology leap, resulting in a completely new solution.
The Extensible Processing Platform (EPP) is an example of this; it enables a technology-leap, ahead of what is currently available from integrated device manufacturers (IDMs) and achievable from traditional FPGA technology. In terms of achieving the best system solution in terms of power consumption and performance, EPP outperforms contemporary configurable technologies, while still delivering greater flexibility and faster time to market than its fixed-function alternatives.
More than an FPGA
The FPGA has been very successful in displacing ASSPs and ASICs, particularly in two-chip implementations where an FPGA sits alongside a general purpose processor.
But as an engineering solution, a two-chip implementation will sometimes fail to match the performance of a fully integrated system-on-chip (SoC). However, for reasons already highlighted, a traditional SoC may not always meet the specific requirements of system engineers. To address this, Xilinx has developed the Zynq-7000 family of Extensible Processing Platforms.
Fundamentally it is a multicore processor with the capability to extend the architecture using customised accelerators and peripherals, implemented in hardware. This is achieved through a combination of an industry-standard multicore processing platform that is fully integrated alongside programmable logic, connected directly to the processing system through an optimised AXI bus interface.
For the first time this allows the performance requirements of a specific application to be met using a single-chip solution without compromising flexibility, or risking time-to-market. Using the Programmable Logic, hardwired accelerators become part of the processor sub-system. Using a high-speed AXI interface to connect the two not only guarantees low latency but gives peripherals DMA access to the processor system, enabling a new paradigm in autonomous peripherals.
This builds on an emerging concept within high performance processors that allows peripherals to operate without the intervention of the host processor, thereby maximising performance and power efficiency. This concept takes on a new dimension when the peripheral itself is configurable and implemented in programmable logic fabric.
As the EPP is fundamentally an industry-standard processing system, software engineers can use their preferred IDE. Similarly, using their own familiar FPGA tool flow, hardware engineers are now able to implement processor extensions directly alongside the processor, connected through a high bandwidth AXI bus. With 3000 connections between the processing system and the programmable logic fabric, this can reach well above 20GBytes/s.
Common Processing Platform
At the heart of the Zynq-7000 family, and constant across all family members, is the ARM dual core Cortex-A9 MPCore processing system. A key difference between the Zynq-7000 family and FPGAs with embedded processors, such as the Virtex-II Pro which features embedded PowerPC cores, is that the ARM processor system in the Zynq-7000 family is able to boot independently of the FPGA. This has a number of benefits but it also means that from a software engineer’s point of view, the Zynq-7000 device looks, feels and behaves just like a general purpose multicore processor. This allows a level of productivity that can only be delivered by a new class of device such as the Zynq-7000 EPP; significantly different from any other form of embedded platform.
From a software engineer’s perspective, the dual-core ARM processor system can operate as a single-core or dual-core device, in either symmetric or asymmetric multicore processing modes. This is supported by boot profiles that are accessible and customisable from within the software design flow, allowing the processing platform to operate completely separately from the programmable logic fabric and, in fact, take control over the fabric. This offers much more flexibility than any other ARM based processing platform available today.
As a full implementation of the Cortex-A9 MPCore, the processing system runs at up to 800MHz and includes single and double-precision floating point support, as well as ARM’s NEON extensions. The processing system is supported by completely integrated internal L1 and L2 caches (32kbyte and 512kbyte unified, respectively), along with 256kbyte of on-chip memory and integrated memory controllers supporting DDR3, DDR2, LPDDR2, 2xQSPI, NOR and NAND Flash.
A range of common peripherals are also integrated and memory mapped at boot time, including eight DMA channels, two USB 2.0 with OTG support and DMA, two tri-mode Gigabit Ethernet ports (also with DMA), two SD/SDIO (also with DMA) and a range of communication ports (two CAN, two SPI, two I2C and two UART) and four 32bit GPIO. The open standard interconnect enabled by AXI also supports cache coherency for additional soft core accelerators that may be implemented in the programmable logic fabric.
This represents a complete processing system that, as mentioned, is available from boot, without any intervention from the programmable logic fabric necessary to support it. It is this ability to boot and run that makes Zynq-7000 EPP a completely new class of device, one that will convincingly meet the challenges now facing the embedded community.
Unique to this ARM based processing system, however, is the ability to extend the processor’s capabilities to include new features and functions, implemented in the programmable logic fabric. These devices also support partial reconfiguration, enabling the programmable logic fabric to be configured to provide different processor extensions or hardware acceleration when needed, without stopping either the processing system or programmable logic fabric. Run-time reconfiguration is a powerful feature that introduced a new level of flexibility to the SoC domain, allowing the device to physically change depending on the application’s dynamic needs.
Application-specific extensions
Extensible processors are commonly only available to processor licensees (companies developing their own ASIC, or ASSP manufacturer developing new generation of ASSP products), to develop devices targeted to a specific application. Developing such specific instructions is a non-trivial task and often requires deep involvement from the IP provider. Therefore this is usually limited to applications that really need the performance enhancement that such custom instructions bring.
This gives ASSP providers a performance advantage over a general purpose processor, even when combined with an FPGA in a traditional two-chip solution. The Zynq-7000 family effectively overcomes the challenge of creating custom extensions while giving the system engineer the ability to create their own ASSP, using what is arguably the world’s most widely adopted embedded processor as the basis for an accelerated, custom and application-specific solution that would, by definition, otherwise only be available as an ASIC or ASSP. It is the ability to create a truly application-specific single chip solution that will enable the ‘design-to-market’ paradigm in embedded electronics.
This will encompass a wide range of new applications that aren’t currently best served through ASSPs or general purpose solutions, for instance the increased use of cameras in applications such as driver assistance, factory automation or surveillance systems. Processing video data streamed from one or multiple cameras is an emerging requirement and one that requires a significantly greater level of compute power than is available from today’s solutions. The ability to extend the processing platform with programmable logic accelerators developed specifically to process video streams in real-time, including the emerging use of video analytics, is just one example of how the configurability of the Zynq-7000 EPP will be used.
Software defined radio is another growing trend that demands greater processing power and optimised solutions. The complexity of signal processing often dictates the use of massively parallel hardware resources, which are particularly difficult to commercialise in a general purpose device. The EPP is ideal in this application, as its single-chip solution maximises the processing bandwidth in both the processing system and the programmable logic fabric.
Memory mapped extensions
As the processor system is connected directly to the programmable logic fabric through the high-speed, low-latency AXI bus, any hardware feature implemented in the fabric becomes addressable by the processing system, literally becoming part of the processor and residing as a memory mapped peripheral.. As a result, the low latency offered by the AXI bus interface will allow the EPP to meet the performance demands of many real-time end-applications, such as motor control, that would be difficult to accommodate using an FPGA with an embedded processor that isn’t as well integrated.
The ARM processing system used in the Zynq-7000 family is built around a dual Cortex-A9 MPCore processor, which feature the latest ARMv7 instruction set. This is part of ARM’s ‘Application’ processor range within the Cortex family and its instruction set is actively supported by a number of leading development tool vendors like Lauterbach (Trace32)and ARM’s (Design Suite 5) and many more. It also has the support of many popular operating systems, including Linux and its derivatives such as Android, but also OSE, VxWorks and many more.
While the expansive ARM eco-system makes the Cortex-A family one of the best supported licensable architectures available today, a key element of the Zynq-7000 family is the design support provided by Xilinx. Hardware engineers can use the Xilinx Platform Studio (XPS), the Embedded Development Kit (EDK), while the associated Software Development Kit provides the tools embedded software developers need to achieve maximum productivity without a learning curve.
These tools enable a crucial part of the processor design flow and are the same tools that currently support the PowerPC and Microblaze cores. Now they have been enhanced to support the ARM processing system in the Zynq-7000 family. Any custom hardware developed and implemented in the fabric can be imported in to the EDK, which adds a wrapper that enables it to connect directly to the AXI bus. Once this wrapper is added, it can be utilised through the software development kit and mapped in to the processor system’s memory map. This is applicable to existing FPGA function libraries as well as new hardware functions.
This tool flow effectively provides an automated Board Support Package (BSP) for a custom SoC, requiring only the drivers to be written to utilise hardware-accelerated functions. It is this design-to-market concept that will enable application-specific SoCs to be developed without the risk associated with developing an ASIC, or selecting an ASSP, while removing the performance issues associated with a two-chip solution.
The Zynq-7000 Extensible Processing Platform represents a new dimension in embedded design, delivering unprecedented performance and flexibility to the engineering community and creating opportunities for equipment manufacturers to really manage the risk in product development.
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