See also: Our roundup of the latest news from the IEEE ISSCC (International Solid State Circuits Conference), San Francisco
Once a year at the International Solid-State Circuits Conference (ISSCC) in San Francisco, the IEEE pulls together the best of recent chip-based circuit designs both analogue and digital. Steve Bush picks a few of the most interesting ideas from hundreds of papers.
Digital circuits
From Harvard University comes an all-digital CMOS temperature sensor for on-die thermal monitoring of microprocessors.
The circuit makes use of the temperature dependency of inverter delays, sending an edge through two parallel paths. One is a wire and the other is a string of inverters. At the end, a time-difference-to-digital converter paths measures the difference.
The key advantage of the technology is that the slope of the delay/temperature curve is almost constant, so all calibration is done at one temperature. 5,000sample/s are possible, power dissipation is 1.2mW and errors are within +/-2.3°C.
Microprocessors
Intel described some of the problems found when designing 45nm processors (pictured below). One issue is increased soft errors, leading to the inclusion of error-correction code in internal memories that corrects double-bit errors and detects triple-bit errors.
A processor incorporating eight dual-threaded 64bit x86 cores, a large shared L3 cache, 16 phase-locked-loops, and eight delay-locked-loops was described - as was coherent point-to-point scalable interconnect that increases off-chip bandwidth up to 6.4Gtransfer/s over a conventional copper bus.
Memory
Samsung presented a 4Gbit 56nm CMOS DRAM, and an 8Gbit DRAM made by stacking four die and joining them with chip vias.
Not to be out-done, Hynix described DDR2 DRAM for mobile applications that transfers data at up to 4.3Gbyte/s while running on 1.35V.
For 3D video, Qimonda revealed a graphics DRAM that reaches 7Gbit/s/pin.
Staying with memory, but this time non-volatile, Intel has a 32Gbit NAND flash in 34nm CMOS. This multi-level-cell chip has a read time of 50µs, programming time of 900µs, and write throughput of 9Mbyte/s.
Engineers from Sandisk and Toshiba described a 64Gbit flash, the highest capacity single-chip flash yet reported. In 43nm CMOS, this memory has 4bits per cell and 5.6Mbyte/s write throughput.
In an almost unbelievable feat of integration, engineers from Keio University and University of Tokyo claim to be able to stack up to 64 chips, that communicate using inductive-coupling.
Demonstrated in 0.18µm CMOS, the wireless interface is said to halve power consumption, divide I/O area by 40, and still achieve 2Gbit/s data rate.
Off the wall
In a genuinely useful piece of spintronics, engineers from European lab CEA, Hitachi, and STMicroelectronics built a 13GHz spin torque RF oscillator based on magnetic tunnelling junctions that is 50x smaller than the equivalent LC oscillator, and tunes over 85% of its frequency compared with 15% for LC types. Measurements over one minute show phase jitter of 36ps(RMS) with the oscillator set at 7.36GHz. The required stack of magnetic layers has a footprint only 90nm across and is constructed by sputtering.
In an another example of alternative engineering, this time a demonstration of what is possible without fibre-to-the-home, engineers from the University of Pavia and Marvell described a fully-integrated VDSL2 interface which delivers 200Mbit/s to the home over 100 meters of plain old copper phone wire.
Organic electronics
Away from silicon, Belgium's IMEC, Polymer Vision and TNO Science and Industry together describe the first organic RFID tag to hold 128bits of data - an information content similar to low-end silicon RFIDs.
It is claimed that such organic transponders could be printed on milk bottles and similar low-cost items as sophisticated bar codes.
German firm PolyIC demonstrated an organic RF tag with both n and p-type transistors. Almost all organic electronics are p-type only.
For the n-type semiconductor, PolyIC used ActiveInk N1200 from Polyera.
Combining silicon and organic electronics, the University of Tokyo and the Max Planck Institute have invented a foil sheet able to map EMI.
The idea is to wrap the object under test in the sheet, which will then measure emissions through it.
Built as a flexible foil, the sheet has organic CMOS circuits wired to silicon chips using stretchable interconnects.