Digital designers have long reached for an oscilloscope as the tool of choice for debug. As FPGAs have become the centrepiece of digital design, the need to quickly debug systems that include programmable logic is stronger than ever.
Traditional oscilloscope technology has not kept up with functional debug of FPGAs, but mixed signal oscilloscopes (MSOs) can deliver the capabilities needed.
MSOs offer the same feature set as traditional oscilloscopes for measuring signal integrity, jitter, and signal characterisation. Designers can choose between versions that have two or four analogue input channels and they come in bandwidths ranging from 300MHz to 1GHz.
These capabilities are important for checking signal parametrics. For example, a designer can readily change I/O standards and drive strengths using Xilinx FPGA Editor and measure the real-world I/O characteristics using an MSO's channels.
ATC2 cores allow design teams to quickly switch which signals are connected to pins for measurement. Each core can be parameterised with just one signal bank or as many as 64.
The major difference between MSOs and traditional digital signal oscilloscopes is the addition of 16 digital asynchronous sampling channels on the MSO. Design teams can choose how fast these digital channels sample. The digital channels offer deep memory storage that is independent of the analogue channel memory storage.
The capabilities of the digital channels can be employed in a number of ways that are particularly valuable for teams developing systems that incorporate FPGAs.
Bus triggering and display
Traditional oscilloscopes provide digital triggering capabilities that allow them to trigger on patterns across the analogue channels. So with a four channel oscilloscope a design team can trigger on a single pattern that is up to four signals wide.
Debug often requires looking at busses using a specific event as the trigger condition. Using an MSO's digital channels, designers can trigger on a digital pattern up to 16 signals wide. This can be a powerful capability when looking at a state machine, an embedded microcontroller, or a data bus. Users can also trigger and capture measurements across all four analogue channels, extending the trigger width up to 20 signals.
While the digital channels can be used to make strictly digital measurements, their capabilities are best employed for looking at problems that are both functional and parametric in nature. For example, triggering on a digital bus and having this trigger condition arm the scope measurement.
Extensive internal visibility
In order to access internal signals, design teams typically use the route out approach to bring signals to pins that can be probed using an oscilloscope.
Using traditional oscilloscopes, designers have access to either two or four signals at a time. This narrow signal visibility can complicate debug as a number of problems require simultaneous visibility across a higher number of signals.
To access new signals the designer must change the design, re-synthesise, and run a new place and route to make signals accessible to the oscilloscope. This process can take hours.
With the digital channels of an MSO, a designer has visibility of up to 16 internal FPGA signals at a time.
The power of the MSO's digital channels can be further extended when combined with on-chip technologies such as Xilinx ChipScope Pro and Agilent FPGA dynamic probe.
ChipScope allows design teams to incorporate an Agilent debug core (ATC2) into FPGA designs. This provides an easy way to route signals to pins, enables a faster set up of the MSO, and allows the user to quickly measure new groups of internal signals. This capability extends the reach of the 16 digital channels into the FPGA design.
Timing cores
ATC2 cores can be configured as either timing (asynchronous) or state (synchronous) cores. Both types of cores are supported with the MSO.
Xilinx Core Inserter injects a core into a design post synthesis and before place and route. If the designer specified a timing core, the place and route tools do not put any flops between the signal being probed and the output pin.
The routing of the signal to pin for measurement is treated as a false path. This allows the place and route tools to ignore any speed constraints associated with routing a specific signal to a pin.
The timing core includes a JTAG controller, but the controller typically runs very slowly (less then 5MHz) as it is only used for small information exchanges such as selecting a new signal bank.
Timing cores can be effective as they allow a user to look at signals across multiple clock domains or at anomalies that have a duration less than one clock cycle. The primary trade-off associated with timing cores is that skew will exist between signal paths.
State cores
Traditional oscilloscopes, as well as MSOs, provide asynchronous acquisition. Samples are stored using an adjustable clock reference internal to the scope. This can make it difficult to accurately capture and decipher synchronous events as the instrument captures invalid transitions between clock cycles.
A more effective way of capturing synchronous information on a single clock domain is to parameterise the ATC2 core as a state core.
A state core will have minimal impact on design timing due to its pipelined architecture. A total of four flops are placed between the signal being probed and an output pad. The design tools place the first flop as close as possible to the signal being probed.
The additional three stages of pipelining allow the signal three clock cycles before reaching the output pad. The pipelined architecture of the ATC2 core allows the place and route tools to have a much greater probability of meeting the original timing goals of the design.
As the core is synchronous, the place and route tools eliminate skew between signal paths.
The primary trade-off with a state core is it works with a single time domain. Using the state core approach, designers that need to measure across clock domains can do so by inserting multiple state cores. The MSO can access multiple ATC2 cores, one at a time, in a single FPGA or distributed across multiple FPGAs on a single scan chain.
The MSO's digital channels provide exclusively asynchronous acquisition. For FPGA debug, there is a method for allowing the MSO to display synchronous measurements, even though the initial acquisition occurs asynchronously.
The ATC2 state core outputs a clock signal and signal states synchronous with the clock. MSOs digital channels acquire this pre-formatted state information. Then the MSO post processes this measurement using a state display feature that allows the user to specify one signal as the clock. The MSO filters out to all transitions between valid states. This gives the capability of making synchronous measurements internal to the FPGA.
The reprogrammable nature of FPGA technology makes rapid iterative real-world debug a great companion to simulation. As FPGAs become even more sophisticated the need for efficient internal visibility increases.
Mixed signal oscilloscopes provide unique measurement capabilities that align with the needs of teams designing systems that incorporate FPGAs. Applications that help engineers exploit the digital measurement capabilities of MSOs are a catalyst for shorter development cycles and higher quality designs.
Joel Woodward is manager of development tools, EDA, at Agilent Technologies