A ‘design fab’ in India offers custom memory design for SOCs to get over the second order device effects that plague sub-65nm compiled embedded memories.
The company, called Nanopower, is backed by Silicon Capital, the VC house set up by Lattice Semiconductor’s founding CEO, Rahul Sud.
"We’re doing it the old-fashioned way," Sud told EW, "sometimes you can have 15 to 20 different types of memory on an SOC. Compiled memories are reasonably reliable at 90nm but, at 65nm and 40nm second order device effects and process variations are very pronounced. So a customer says: ‘I want these memories’ and we provide a full custom design of every memory on the SOC."
The customer gets full design transparency of the memory as opposed to a compiled black box.
The CEO of Nanopower, Gopal Dharmaraj, explains: "Can you imagine an analogue or RF circuit generated automatically by a software compiler which works reliably over all process variations, temperature and voltage conditions? With second order device physics effects now becoming first order effects, and process variations now a very significant percentage of the process/device parameter, the time has come when a memory, to be fully reliable, needs to be a full custom, manual design."
"ARM and Virage are supporting 50 fabs - either foundries or IDMs" adds Sud, "each fab has three to five tech nodes, each node has three to five flavours. Characterising every possible memory instance for every possible foundry and every possible node and every possible flavour equals two million simulations per day."
Nanopower’s answer is to go back to basics – to full custom manual design.