The 450mm wafer transition could cost $40bn says CEA-LET's Michel Brillouet. SEMI puts the cost at $25-40bn with much of it centred at the Global 450 Consortium (G450C).
Tom Jefferson, 450 programme manager at Sematech says that, by mid-2013 to early 2014, a complete 450mm production line will be established at Albany containing 50 different tool types.
The objective of the pilot line will be to develop data to support the purchase of production-line tools and it is unlikely that non-participants in G450C will be favourably considered for 450 production lines.
It is thought that, when 450mm reaches production, significant 30mm development will cease for tool suppliers due to limited resources and poor return on investment.
"Some equipment suppliers may choose to stay off 450mm and focus on specialty development on 300mm platforms, but the 8nm node is likely to be the 450mm equivalent of 65nm’s ‘300mm only’ moment," says SEMI, adding "furthermore, the ‘Post CMOS’ era will likely be exclusively on 450mm wafers."
Once 450mm is developed, spare capacity in 300mm will emerge, encouraging a migration from 200mm production, impacting the viability and competitiveness of both 200mm and 300mm fabs, says SEMI. In 15-20 years, even low volume, mature technologies in MEMS, power and analogue could migrate to 450mm fabs.
How the EU chooses to support the semiconductor industry through the coming years is being evaluated.
There are divergences of interest across the industry: European IC manufacturers are currently not planning 450mm investments; many equipment and materials suppliers see an opportunity, but many suppliers see the 450 R&D draw threatening long-term profitability and current customers.
Similarly, European consortia and R&D organisations see both an opportunity and a threat as - unlike current 300 mm process development which occurs at multiple locations around the globe - near-term 450 development seems likely to be exclusively conducted at the G450C site in New York.
"With $2-3bn necessary for a stake in a 450 development fab capability, it is unclear whether both wafer size transition, next node scaling, new transistor technology, and 3D IC could be simultaneously be funded," says SEMI.
CEA-LETI's Brillouet says the EC’s options are: help develop 450 and forget all More-than-Moore projects; forget 450 and concentrate on other process technologies such as 3D, EUV, etc, and support R&D by equipment and material suppliers without a European production or pilot development lab.
Hans Lebon, VP Fab & Process Step Development at Imec says: "Wafer size transition accelerates industry consolidation." Estimating the cost of the transition at $25bn, Lebon says the 300mm wafer size transition "wasn’t cost effective." One of the ways to manage costs will be through "fewer equipment platforms." Imec is still trying to formulate a role in 450, and claimed there "still was a long journey to go."
Sematech’s Jefferson says over 40 companies are participating in the programme, defects per wafer have been reduced from more than 3000 to less than 200, and that effective SEMI standards have been developed to enable development.
How much of the $4.4bn committed to the Albany project is already-committed IBM money for other (non-450) advanced chip design and technology development was not verified, says Sematech’s Jefferson.
The Albany 450mm fab site has been prepared and walls are going up on the fast-track project, says Jefferson, nanoimprint technology from EV Group will be used as the "stopgap measure" in lieu of a workable EUV solution.
The pilot line will include 50 types of tools, many with more than one supplier contributing. The goal of the pilot line will be to develop a database that will be used to support production tool purchasing.
Participants in the program will benefit from access to patterned and non-patterned wafers, shared metrology and Multi Application Carriers (MACs), shared consortium staff resources, data sharing, and "financially leveraged business partnerships" with consortium partners.
Suppliers who do not participate in the programme will be lower on the priority for access to test wafers. The impression left was that not participating in the program will lower the probability of participation in production line rollouts by consortium partners.
The consortium is expected to have different intercept points for logic and DRAM, but the "expectation should be for 10nm and beyond," says Jefferson, and the timing for the second half of 2013-early 2014.
Geert van der Zalm of Bosch Rexroth says: We may need to rethink tool architecture, such as using inverted linear motor to enable inline vacuum transport that has been proven useful in the solar industry."
Michael Schilp, Zimmermann & Schilp Handhabungstechnik, has a radically alternative approach to non-contact 450 mm wafer handling using ultrasound.
Mike Cooke from Oxford Instruments says the first tests on 450 PECVD SiO2 processing have so far yielded only a 4.2% uniformity across all points. In induction coupled etch plasma, a +/- 10% uniformity across a 450 wafer has been achieved (half of the non-uniformity at the wafer edge), that according to Cooke was "not good enough, but a useful start."