For space use, the University of Arkansas has developed a differential amplifier that operates from -180 to +120°C.
"This and several other designs focus on wide-temperature operational characteristics of sensor-based, signal-processing circuits. Some of our designs have been tested as fully operational down to 2K," said Professor Alan Mantooth.
"This one is the first fully differential amplifier circuit designed specifically for extreme temperatures, including temperatures in the cryogenic region."
The 3.3V design uses only SiGe heterojunction npn and PMOS transistors, as they show better wide temperature and radiation performance when compared with pnp and NMOS devices. The team selected IBM's 5AM BiCMOS process to make the amplifier.
Architecturally it has a NPN differential pair input stage feeding source follower buffers which drive a PMOS differential pair output stage.
Left uncontrolled, the common-mode output voltage drift of both the input and output stage would be too high over the extreme temperature range.
Two separate feedback circuits counter this, one for the input and one for the output. Each monitors common mode voltage, and restrains it by altering the bias point of the differential pair's active loads.
The feedback circuits each consume only three NPN and two PMOS transistors and together allow the complete amplifier to have an input common-mode range of 1.0-2.3V.
These figures come from modelling.
In practice, the fabricated chip maintains an output voltage swing of 0.45-2.57V and an input common mode of 0.5-2.5V over -142 to +125°C, and more limited operation down to -180°C.
Simulated open-loop gain is 72dB with a unity gain frequency around 130MHz.
While computer predictions for the amplifier show reasonable agreement with the resulting silicon, said Mantooth, they would have matched more closely if transistor models were available that took into account effects that are generally neglected except at cryogenic temperatures - for example the narrowing of beta vs. collector current as temperature decreases.
The team is now working on such models.
On the die, each stage is surrounded by a guard ring to decrease latch-up vulnerability and improve isolation.
All transistors, particularly those in the input stage, are carefully matched and positioned on the die to decrease offset voltages.
Dummy features are included to improve the uniformity of polysilicon etching at crucial points.