Silicon Labs has announced an all-CMOS oscillator to compete directly with crystals.
Dubbed Si500, "it generates any frequency from 900kHz to 200MHz and phase jitter is 2ps(RMS) maximum, 1.5ps typical", said the firm. Period jitter at 100MHz is typically under 0.8ps.
Stability options range from +/-100 to +/-150ppm over 0-70 deg C. "The stability is guaranteed over a 10 year lifetime," said marketing manager James Wilson.
LVPECL, LVDS, HCSL differential output versions are available, as well as single-ended ‘CMOS’ and SSTL outputs.
Inside, the reference is a compensated 4GHz LC oscillator with, according to Wilson, the inductor and capacitor in the metal layers.
"By eliminating the mechanical resonator used for frequency generation, the Si500 also provides high immunity to the shock and vibration that plagues traditional crystal oscillators," claimed Silicon Labs.
This is followed by a divider to produce the required output.
The internal power rail is regulated, with external supply voltage options of 1.8, 2.5 and 3.3V available. As with the frequency, supply voltage has to be specified on order as it is factory set.
The LVDS version has the lowest power consumption at 11mA. Of this, the oscillator, compensation and divider together take 8mA.
The single-ended ‘CMOS’ output version consumes 16mA and 28mA is needed by LVPECL variants.
One pin on the IC can be factory set to either: stop the driver, tri-state the output, or power the chip down to 1.7mA.
Applications are foreseen in PC peripherals, LCD displays, servers and storage applications, as well as portable devices that can stand the power draw - test and measurement equipment for example, said Wilson.
Package is either a four or six pad 3.2x4.0mm DFN package. The chip is sampling now with volume production planed for the last quarter of this year.