MIPS Technologies has unveiled a new platform strategy for MIPS-based system-on-chips. Called SOC-it, MIPS said the platform strategy will simplify design of high-performance SoCs and accelerate time to market.
The company announced the enhancements to the programme during the Instat Microprocessor Forum in San Jose this week. MIPS first announced SOC-it system controllers four years ago.
“In the past people have done their own design methodologies,” said Allen Watson, product marketing manager for the platform family. “We are trying to shorten the time for people to do designs and also reduce their risk.”
With that in mind, MIPS is designing a set of pre-verified semiconductor components that go around the processor.
“This approach lets the customer concentrate on where he is adding value,” Watson said. The first product to be a part of the approach will be an L2 cache controller, he said.
It is designed to minimise memory latency, and reduce system costs and power consumption. Fully synthesisable, the SOC-it L2 Cache Controller works with all MIPS OCP-based cores and uses standard cell libraries and memory arrays. It is available today to early access customers.
Other parts will include a system controller, DDR memory controller, interrupt controller and interrupt devices. In addition, MIPS is offering a hardware abstraction layer where designers can take out or indicate they do not want to use the MIPS-specified IP and choose something else from their favourite IP supplier instead, according to Watson. This allows for the underlying hardware to be changed without affecting software compatibility.
With availability estimated for Q1 CY 07, the SOC-it System Controller uses a crossbar bus structure suitable for low latency and high bandwidth applications, providing an optimal interface to DDR/DDR2 system memory. Additional components include an SRAM controller, interrupt controller and bus controller for off-chip devices such as ROM/RAM memories.