UK start-up Silistix has revealed details of tools that it claims make the advantages of clockless interconnects accessible to all designers.
The EDA firm's CHAINworks software and libraries simplify the interconnection of intellectual property (IP) blocks and save power and area by generating an interconnect fabric that runs without a global clock. The CHAIN (chip-area interconnect network) flow accepts Verilog and SystemVerilog inputs, and fits into a standard chip development process.
"You define your endpoints, your initiators and targets, and their ports," explained David Frist, v-p of marketing at Silistix. "We take that into our system and allow you to describe, either via scripts or graphically, how those are connected up."
The company was founded in 2003 by the University of Manchester’s asynchronous guru Professor Steve Furber and two of his former PhD students. Its idea is that enabling designers of complex 65nm chips to easily use clockless technology will help them tackle a dominant problem - achieving timing closure.
 |
A test device clocked using CHAIN technology
|
"[With our technology] it’s like you’ve got Lego blocks and you’re just plugging them together to make your system," explained Frist. "By isolating the endpoints you’ll get timing closure on your ARM7, your DSP, your memory controller; timing closure independently on your interconnect, and then you’re done."
Users do not have to learn special scripting languages, they just define the inputs and the Silistix tools generate a structural netlist that represents the asynchronous network. That netlist goes through the usual synthesis.
Verifying clockless designs has been a major issue in the past, and the company intends to make a further announcement next week about a production verification technology that enables the generated interconnect to be subjected to ATE testing.
www.silistix.com