Intel has revealed a 1.28Tflop single-chip number cruncher at the International Solid-State Circuits Conference (ISSCC) this week in San Francisco.
The 65nm 100 million transistor 4GHz device includes an 8x10 array of 'processing engines' (PEs), each consisting of two 32-bit floating-point single-precision multiply-accumulators (FPMACs), memory, and a five-port crossbar router that hooks the engine to the on-chip network. This mesh-like network runs between the rows and columns of engines at 32Gbyte/s. The total switch bandwidth is 80Gbyte/s.
Each FPMAC can accumulate in a single cycle, and is connected to 3kbyte of instruction memory and 2kbyte data memory. A 96bit VLIW instruction includes up to eight operations/cycle.
With both FPMACs occupied, each engine operates at up to 16Gflop/s.
Power consumption is reduced by fine-grained clock gating and body biasing. Sleep transistors occupy 5.4 per cent of the chip area and cut performance by four per cent while gating 90 per cent of FPMAC logic and 74 per cent of each PE.
Simulations predict that at 110°C, the chip will run at 3.13GHz (1Tflop) at 1V and 4GHz at 1.2V.
Power consumption estimates are 98W at 1V and 181W at 1.2V. 310Gflop at 0.6V (11W) equates to 27Gflop/W.
The chip occupies 275mm sq. and has 8,390 solder bumps which attach it to a 14-layer organic package. Each engine within this is 1.5x2.0mm.