AMD has described its quad-core x86 processor at the International Solid-State Circuits Conference (ISSCC) in San Francisco.
Each of the four cores has its own 512kbyte level 2 cache and a 128-bit floating point unit.
The cores share 2Mbyte of on-chip level 3 cache and a memory controller that supports up to four 16-bit HyperTransport links and a dual-channel 128-bit DDR2/DDR3 interface.
A 65nm silicon-on-insulator process is used for producing the near 450 million transistor device, with dual stress liners and a silicon germanium (SiGe) process is used to speed up the pFETs. Eleven layers of copper and low-k dielectrics connect the device.
At 95°C, modelling suggests the processor will run at between 2.2 and 2.8GHz at 1.15V. Each of the four cores include eight temperature sensors. The on-chip northbridge contains a further six.
Memory interface is 400 to 800Mbit/s from a 1.7-1.9V supply for DDR2, and 800 to 1,600Mbit/s from 1.4-1.6V for DDR3.
The HyperTransport interface supports legacy HT1 and 2 modes as well at HT3 at 2.4Hbit/s with a peak of 5.2Gbit/s.