Electronics Weekly Magazine
Loading

Sign-up for newsletters:

Electronics Weekly newsletters - Sign up for Made By Monkeys, Mannerisms, Gadget Master and Daily and Monthly newsletters

Lattice and Cavium test SRIO for 3G basestation links

Richard Wilson
Wednesday 12 May 2010 08:49

Lattice Semiconductor is planning interoperability testing with Cavium Networks processors and its FPGAs as part of a drive on the 3G/4G mobile basestation market.

The link tests between LatticeECP3 FPGAs and Cavium Networks' OCTEON II CN63XX processors will use the Serial Rapid IO (SRIO) Specification 2.1 link.

"We are working to introduce future bridging applications for the OCTEON II and our ECP3 family, including SRIO to CPRI, SRIO to PCIe and SRIO to SGMII," said Ted Marena, director of business development for Lattice.

SRIO offers low latency which is needed in wireless basestations and routers. The OCTEON II processor integrates SERDES-based I/Os, including SRIO.

"The addition of the SRIO interface in the OCTEON II processors, along with the wide variety of other standards-based interfaces, provides a new low-latency connectivity option," said Tasha Castañeda, Senior Strategic Alliance Manager, Cavium Networks. 

Lattice's ECP3 device also has SERDES I/Os capable of supporting Serial RapidIO 2.1 using a soft core.

Supplied by Praesum Communications, the core supports 1x, 2x and 4x lane configurations at up to 3.125Gbit/s lane speeds.

Lattice has also licensed the core from Praesum, and has full rights to use and sub-license it.

"RapidIO has won broad acceptance in wireless infrastructure applications, where it is used as a primary interconnect for DSP clusters in baseband processing," said Lattice. "The combination of core and FPGA will allow customers to develop infrastructure solutions for 3G, LTE and WiMAX.

The core implements physical layer, transport layer, maintenance transaction handling and error management extensions, as well as providing infrastructure support for external logical layer functions.

It supports software implementations of control plane oriented functions such as doorbells and messages, and is backward compatible with the v1.3 specification.

The ECP3 FPGA family has five devices with multi-protocol 3.2G SERDES, DDR1/2/3 memory interfaces, and cascadable DSP slices.

Cavium and Lattice said they will announce updates as they become available.

 

Comments powered by Disqus

Share the content

Most Viewed

Products

Related Jobs

Resources