Configurable processor designer ARC International has developed a new standard version of its architecture that is aimed specifically at high definition TV.
The VRaptor Media Architecture is a version of ARC’s high end 750D core where ARC has added new instructions to handle multiple 128bit single instruction, multiple data (SIMD) instructions to get the performance necessary, as well as new dedicated accelerators.
This is the first time that ARC has added additional accelerator block to the architecture, and the company has developed a new interconnect that is calls ‘active communications channel’ for linking these blocks together to get the necessary system performance for decoding images at the 1080I resolution.
For an SD resolution H.264 decoder, one 750D core would be coupled with one media processor. This would operate at 200MHz and take up a few square millimetres of silicon.
An HDTV decoder would be a series of 750D CPUs with hardware accelerators and another 750D with multiple media processors to do the pixel processing in a total of around 900,000 gates, which is comparable to a hardwired decoder, and would occupy 20 sq mm (a chip less than 5x5mm) in a 130nm process.
Arc’s VRaptor technology, not to be confused with the Vraptor.org open source software project for programming World Wide Web applications, was launched at the Fall Processor Forum in California on Monday, with the patents on the communications technology filed the previous Friday.
The VRaptor core will be combined with the audio subsystems already shipping from ARC for a complete media subsystem for system-on-chip developers early next year.
Sci-worx in Germany has been working on an HD decoder block for SoC developers using four of the Xtensa LX configurable core from Tensilica.