ISSCC panel explores future of RF CMOS

An evening discussion session at the International Solid State Circuits Conference in San Francisco last week explored what future - if any - RF circuitry has in the ever-shrinking world of CMOS. Invited speakers approached the question from the device, model, circuit, and chip levels.

Leading off, Philips Electronics device expert Maarten Vertregt offered a quick tour of the transistors that will be available to RF designers as CMOS continues to scale. The good news, according to Vertregt, is that scaling will continue to produce faster devices - at higher power. "Yet by relaxing the transistor dimensions it is possible to get a better power/performance ratio from these processes," he said.

But then Vertregt cited some issues. Variation, for one. "We can see a variation of plus or minus 10 per cent in maximum frequency within a single reticle area," he said. "Across a whole wafer, the variation can be plus or minus 20 per cent." Such variations make necessary digital calibration and correction circuits, he commented.

Then there's leakage. Not only is the much-discussed sub-threshold channel leakage an issue - and very dependent on temperature - but in advanced processes, engineers also must consider gate leakage from tunneling and diode leakage. Vertregt said that the PSP model being proposed by the Compact Modeling Committee does a good job with these leakage currents. But additional issues that demand attention include self-heating of the devices.

Sally Liu, RF modeling manager at TSMC, then took over with a view from the model perspective. In a detailed analysis, she discussed how the models necessary for RF differ from the analogue models, which again are more complex than the models used for digital design.

"The sweet spot for RF design is near threshold," she observed. "That's an area that is ignored by the logic designers." In addition, issues like flicker noise and white noise must be modeled.

Echoing Vertregt's statement that RF designs would have to employ highly regular layouts, Liu warned that models would be highly layout-specific. The position of guard rings, stress effects - which will change channel mobility whether they are intentional or not - and even the ion scattering that, during formation of the well, can shower adjacent transistor structures, will all cause effects significant to the RF designer.

Liu cited some good news - the availability of multilayer copper interconnect stacks will make possible relatively high-Q inductors and capacitors. Too many, perhaps; Liu said more than 200 ways exist to lay out a capacitor using two metal layers. Electromagnetic modeling tools and scalable models that can work across a wide range of device sizes will be needed, as well as models of temperature coefficients.

On the subject of interconnect, Liu said that variations are a serious problem. Not only are there numerous sources of very significant variations, but above 10GHz inductance becomes an important consideration, and at some point transmission-line models are mandatory. Yet these models must comprehend variations. And they must provide accurate statistics early in the life of the process, before enough time has passed collect adequate statistics from production silicon - a serious and unresolved issue.

Behzad Razavi, a renowned circuit guru from the University of California, Los Angeles, then gave a short clinic on yet another level of difficulty: circuit design in the presence of very low supply voltages, decreasing transistor output impedances, and increasing gate leakage.

In a series of modifications to existing circuit designs that bordered on legerdemain, Razavi illustrated how each of these issues could compromise the performance of a sample circuit, and then how elegant circuit modifications could minimise the problem.

Finally, Bill Krenik of Texas Instruments offered a proof point at the chip level that in fact RF integration onto a CMOS SOC could be viable. Krenik described TI's "single-chip" GSM handset SOC, which includes much of the low-voltage RF circuitry on the same chip with the baseband and control functions.

Pointing out that TI is planning a whole series of such integrations to serve such markets as CDMA phones, GPS receivers, and the like, Krenik argued for the viability of the technology despite the design challenges.